FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 103

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

Programmed I/O - Transfers from the Host to
the FIFO
In the forward direction an interrupt occurs when
serviceIntr is 0 and there are writeIntrThreshold or
more bytes free in the FIFO. At this time if the
FIFO is empty it can be filled with a single burst
before the empty bit needs to be re-read.
Otherwise it may be filled with writeIntrThreshold
bytes.
writeIntrThreshold =
(16-<threshold>) free
bytes in FIFO
103
An interrupt is generated when serviceIntr is 0 and
the number of bytes in the FIFO is less than or
equal to <threshold>. (If the threshold = 12, then
the interrupt is set whenever there are 12 or less
bytes of data in the FIFO.) The PINT pin can be
used for interrupt-driven systems. The host must
respond to the request by writing data to the FIFO.
completely filled in a single burst, otherwise a
minimum of (16-<threshold>) bytes may be written
to the FIFO in a single burst. This process is
repeated until the last byte is transferred into the
FIFO.
If at this time the FIFO is empty, it can be