FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 132

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

The FDC37M81x offers support for ACPI power
management
management event is requested by an ACPI
function via the assertion of the nIO_PME signal.
In the FDC37M81x, only active transitions on the
ring indicator inputs nRI1 and nRI2, active
keyboard-data edges (high to low) and active
mouse-data edges (high to low) can assert the
nIO_PME signal.
open-drain output.
nIO_PME functionality is controlled by the
configuration registers in logical device number
eight.
LD8:CRC5.0, globally controls PME Wake-up
events.
nIO_PME signal can not be asserted.
PME_En is asserted, any wake source whose
individual PME Wake Enable register bit,
LD8:CRC8, is asserted can cause nIO_PME to
become asserted. The PME Wake Status
register,
LD8:CRC7,
The
When PME_En is inactive, the
events
PME
nIO_PME is an active low
Enable
indicates
(PMEs).
bit,
which
A
PME_En,
PME SUPPORT
power
When
wake
132
source has asserted the nIO_PME signal. The
PME Status bit, PME_Status, LD8:CRC6.0, is
asserted by active transitions of PME Wake
sources. PME_Status will become asserted
independent of the state of the global PME
enable,
CONFIGURATION section for further details.
The following pertains to the PME status bits for
each event.
•
•
See the “Keyboard and Mouse PME Generation”
section for information about using the keyboard
and mouse signals to generate a PME.
The output of the status bit for each event is
combined with the corresponding enable bit
to set the PME status bit.
The status bit for any pending events must
be cleared in order to clear the PME_STS
bit.
PME_En.
Refer
to
the