FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 112

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

The FDC37M81x supports the serial interrupt to transmit interrupt information to the host system. The
serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
Timing Diagrams for SER_IRQ Cycle
A) Start Frame timing with source sampled a low pulse on IRQ1
Note:
Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI
B) Stop Frame Timing with Host using 17 SER_IRQ sampling period.
Note:
Note 1: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
Note 2: There may be none, one or more Idle states during the Stop Frame.
Note 3: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-
PCI_CLK
SER_IRQ
Drive Source
PCI_CLK
SER_IRQ
Driver
H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
bridge hierarchy in a synchronous bridge design.
H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle
around clock of the Stop Frame.
S
FRAME
None
IRQ14
R
IRQ
SL
or
H
T
START
S
Host Controller
IRQ15
START FRAME
H
IRQ15
FRAME
R
1
T
SERIAL IRQ
R
S
IOCHCK#
None
FRAME
112
R
T
IRQ0 FRAME IRQ1 FRAME
T
S
None
I
R
2
STOP FRAME
Host Controller
T
STOP
H
S
IRQ1
1
R
R
T
T
NEXT CYCLE
IRQ2 FRAME
S
None
START
R
T
3