FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 175

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

Note:
Note:
NAME
NAME
NAME
CLOCKI
t1
t2
t1
t2
t3
t4
t5
t1
P C I_ C L K
n R E S E T _ D R V
Tolerance is ± 0.01%
The RESET width is dependent upon the processor clock. The RESET must be active while
the clock is running and stable.
Clock Cycle Time for 14.318MHz (Note)
Clock High Time/Low Time for 14.318MHz
Clock Rise Time/Fall Time (not shown)
Period
High Time
Low Time
Rise Time
Fall Time
nRESET_DRV width (Note)
FIGURE 9A - INPUT CLOCK TIMING
DESCRIPTION
DESCRIPTION
DESCRIPTION
FIGURE 9B – PCI CLOCK TIMING
FIGURE 9C - RESET TIMING
t5
t1
t1
175
t1
t3
t2
MIN
MIN
20
30
12
12
MIN
t4
1.5
t2
t2
69.84
TYP
TYP
TYP
35
MAX
MAX
MAX
33.3
5
3
3
UNITS
UNITS
UNITS
μ s
nsec
nsec
nsec
nsec
nsec
ns
ns
ns