FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 124

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

GATEA20 AND KEYBOARD RESET
The FDC37M81x provides two options for
GateA20 and Keyboard Reset: 8042 Software
Generated GateA20 and KRESET and Port 92
Fast GateA20 and KRESET.
Bit
7:6
5
4
3
2
1
0
Function
Reserved. Returns 00 when read
Reserved. Returns a 1 when read
Reserved. Returns a 0 when read
Reserved. Returns a 0 when read
Reserved. Returns a 1 when read
ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be
driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven high.
Alternate System Reset. This read/write bit provides an alternate system reset
function. This function provides an alternate means to reset the system CPU to
effect a mode switch from Protected Virtual Address Mode to the Real Address
Mode. This provides a faster means of reset than is provided by the Keyboard
controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause
the nALT_RST signal to pulse active (low) for a minimum of 1 µs after a delay of
500 ns. Before another nALT_RST pulse can be generated, this bit must be written
back to a 0.
Name
Location
Default Value
Attribute
Size
8042
P21
0
0
1
1
Port 92 Register
nGATEA20
ALT_A20
124
0
1
0
1
PORT 92 FAST GATEA20 AND KEYBOARD
RESET
Port 92 Register
This port can only be read or written if Port 92
has been enabled via bit 2 of the KRST_GA20
Register (Logical Device 7, 0xF0) set to 1.
This register is used to support the alternate
reset (nALT_RST) and alternate A20 (ALT_A20)
functions.
Port 92
92h
24h
Read/Write
8 bits
System
nA20M
0
1
1
1