FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 156

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

SMI Enable Register
1
Default = 0x00
on VCC POR and
VTR POR
SMI Enable Register
2
Default = 0x00
on VCC POR and
VTR POR
Bit 1 is set to ‘1’ on
VCC POR, VTR
POR, HARD
RESET and SOFT
RESET
SMI Status Register
1
Default = 0x00
on VCC POR and
VTR POR
SMI Status Register
NAME
REG INDEX
0xB4 R/W
0xB5 R/W
0xB6 R/W
0xB7 R/W
This register is used to enable the different interrupt
sources onto the group nSMI output.
1=Enable
0=Disable
Bit[0] Reserved
Bit[1] EN_PINT
Bit[2] EN_U2INT
Bit[3] EN_U1INT
Bit[4] EN_FINT
Bit[5] Reserved
Bit[6] Reserved
Bit[7] EN_WDT
This register is used to enable the different interrupt
sources onto the group nSMI output, and the group
nSMI output onto the nSMI frame in the Serial IRQ
stream..
Unless otherwise noted,
1=Enable
0=Disable
Bit[0] EN_MINT
Bit[1] EN_KINT
Bit[2] EN_IRINT
Bit[3] Reserved
Bit[4] EN_P12: Enable 8042 P1.2 to route internally to
nSMI. 0=Do not route to nSMI, 1=Enable routing to
nSMI.
Bit[5] Reserved
Bit[6] EN_SMI_S: Enables nSMI Interrupt onto
Serial IRQ.
Bit[7] Reserved
This register is used to read the status of the SMI
inputs.
The following bits must be cleared at their source.
Bit[0] Reserved
Bit[1] PINT (Parallel Port Interrupt)
The Parallel Port interrupt defaults to ‘1’ when the
Parallel Port activate bit is cleared. When the Parallel
Port is activated, PINT follows the nACK input.
Bit[2] U2INT (UART 2 Interrupt)
Bit[3] U1INT (UART 1 Interrupt)
Bit[4] FINT (Floppy Disk Controller Interrupt)
Bit[5] Reserved
Bit[6] Reserved
Bit[7] WDT (Watch Dog Timer)
This register is used to read the status of the SMI
156
DEFINITION
STATE
C
C
C
C