MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 53

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

8.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the GP2/AN2/T0CKI/INT/
COUT pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF (PIR1<5>) is set.
FIGURE 8-2:
TABLE 8-2:
 2003 Microchip Technology Inc.
GP2/CCP1
0Bh/
8Bh
0Ch
0Eh
0Fh
10h
1Ah
13h
14h
15h
8Ch
Legend:
Addr
Special Event Trigger will:
• Clear TMR1H and TMR1L registers
• NOT set interrupt flag bit TMR1F (PIR1<0>)
• Set the GO/DONE bit (ADCON0<1>)
Pin
Output Enable
TRISIO<2>
INTCON
PIR1
TMR1L
TMR1H
T1CON
CMCON1
CCPR1L
CCPR1H
CCP1CON
PIE1
Name
Compare Mode
Shaded cells are not used by the Capture, Compare or Timer1 module.
— = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown.
Q
Special Event Trigger
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Capture/Compare/PWM Register1 Low Byte
Capture/Compare/PWM Register1 High Byte
T1GINV
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
CCP1CON<3:0>
P1M1
R
Bit 7
S
EEIE
EEIF
GIE
Mode Select
—
Output
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
Set Flag bit CCP1IF
TMR1GE
P1M0
Bit 6
ADIE
PEIE
ADIF
(PIR1<5>)
—
Match
T1CKPS1
CCP1IE
CCP1IF
DC1B1
CCPR1H CCPR1L
Bit 5
T0IE
TMR1H
—
Comparator
Advance Information
T1CKPS0
TMR1L
DC1B0
Bit 4
INTE
—
—
—
T1OSCEN
CCP1M3
Bit 3
GPIE
CMIF
CMIE
—
8.2.1
The user must configure the GP2/AN2/T0CKI/INT/
COUT pin as an output by clearing the TRISIO<2> bit.
8.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 pin is not affected.
The CCP1IF (PIR1<5>) bit is set, causing a CCP
interrupt (if enabled). See Register 8-1.
8.2.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts A/D conversion, if
enabled. This allows the CCPR1 register to effectively
be a 16-bit programmable period register for Timer1.
Note:
Note:
CCP1M2
T1SYNC
OSFIF
OSFIE
Bit 2
T0IF
—
Clearing the CCP1CON register will force
the GP2/AN2/T0CKI/INT/COUT compare
output latch to the default low level. This is
not the GPIO data latch.
TMR1CS
CCP1M1
CCP1 PIN CONFIGURATION
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The special event trigger from the CCP1
modules will not set interrupt flag bit
TMR1IF (PIR1<0>).
TMR2IF
TMR2IE
T1GSS
Bit 1
INTF
CMSYNC
TMR1ON
CCP1M0
TMR1IF
TMR1IE
Bit 0
GPIF
PIC12F683
POR, BOD
0000 0000
000- 0000
xxxx xxxx
xxxx xxxx
0000 0000
---- --10
xxxx xxxx
xxxx xxxx
0000 0000
000- 0000
Value on
DS41211A-page 51
0000 0000
000- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- --10
uuuu uuuu
uuuu uuuu
0000 0000
000- 0000
Value on
all other
Resets