MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 31

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

3.6.8.2
A Reset will clear SCS bit. The sequence for starting
the primary oscillator following a Reset is the same for
all forms of Reset including POR. There is no transition
sequence from the secondary to the primary oscillator.
Instead, the device will reset the state of the OSCCON
register and default to the primary oscillator. The
sequence of events that take place after this will
depend upon the value of the F
configuration register. If the external oscillator is
configured as a crystal (HS, XT, or LP), the CPU will be
held in the Q1 state until 1024 clock cycles have
transpired on the primary clock. This is necessary
because the crystal oscillator had been powered down
(see Figure 3-9).
During the oscillator start-up time, the system clock
does not come from the secondary oscillator, INTOSC.
Instruction execution and/or peripheral operation is
suspended and INTOSC is disabled.
If the primary system clock is either RC, EC or
INTOSC, the CPU will begin operating on the first Q1
cycle following the wake-up event. This means that
there is no oscillator start-up time required because the
primary clock is already stable; however, there is a
delay between the wake-up event and the following Q2.
FIGURE 3-9:
 2003 Microchip Technology Inc.
System Clock
Note:
CPU Start-up
Peripheral
Program
INTOSC
Counter
OSC1
OSC2
OSTS
Clock
Reset
Sleep
Note 1: T
If Two-speed Clock Start-up or Fail-Safe
Clock Monitor is enabled, the INTOSC will
act as the system clock until the Oscillator
Start-up Timer has timed out.
Returning to Primary Oscillator with
a Reset
2: T
3: T
Q4
PC
OSC
EPU
INT
PRIMARY OSCILLATOR AFTER RESET (HS, XT, LP)
= 32 s maximum
Q1
= 5-10 s
= 50 ns minimum
T
OST
T
EPU
OSC
bits in the
Advance Information
Q1
0000h
Q2
Q3 Q4 Q1 Q2
T
OSC
T
INT
An internal delay timer of 5-10 s will suspend
operation after the Reset to allow the CPU to become
ready for code execution. The CPU and peripheral
clock will be held in the first Q1 following the exit from
low power. The clocks will be released on the next
falling edge of the input system clock. The CPU will
advance the system clock into the Q2 state following
two rising edges of the incoming clock on OSC1. The
extra clock transition is required following a Reset to
allow the system clock to synchronize to the
asynchronous nature of the Reset source (see
Figure 3-10).
The sequence of events is as follows:
1.
2.
3.
4.
0001h
Q3 Q4 Q1 Q2
A device Reset is asserted from one of many
sources (WDT, BOD, MCLR, etc.).
The device resets and the CPU start-up timer is
enabled if in Sleep mode. The device is held in
Reset until the CPU start-up time-out is
complete.
If the primary system clock is configured as an
external oscillator (HS, XT, LP), then the OST
will be active waiting for 1024 clocks of the
primary system clock. While waiting for the OST,
the device will be held in Reset. The OST and
CPU start-up timers run in parallel.
After both the CPU start-up and OST timers
have timed out, the device will wait for one
additional clock cycle and instruction execution
will begin.
0003h
Q3
Q4
PIC12F683
Q1 Q2 Q3 Q4
0004h
DS41211A-page 29
0005h