MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 37
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MCP1726T-ADJZEMF
Manufacturer Part Number
MCP1726T-ADJZEMF
Description
Regulator, Extended Industrial, HVSON, 8-Pin|
Manufacturer
Microchip Technology
Datasheet
1.MCP1726T-ADJZEMF.pdf
(154 pages)
- Current page: 37 of 154
- Download datasheet (2Mb)
4.2.2
Each of the GPIO pins is individually configurable as an
interrupt-on-change pin. Control bits IOCx enable or
disable the interrupt function for each pin. Refer to
Register 4-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR'd
together to set, the GPIO Change Interrupt flag bit
(GPIF) in the INTCON register.
REGISTER 4-4:
2003 Microchip Technology Inc.
bit 7-6
bit 5-0
INTERRUPT-ON-CHANGE
IOC — INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)
bit 7
Unimplemented: Read as ‘0’
IOC<5:0>: Interrupt-on-change GPIO Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1:
Legend:
R = Readable bit
- n = Value at POR
U-0
—
2:
Global interrupt enable (GIE) must be enabled for individual interrupts to be
recognized.
IOC<5:4> reads ‘1’ in XT, LP and HS modes.
U-0
—
Advance Information
R/W-0
IOC5
W = Writable bit
‘1’ = Bit is set
R/W-0
IOC4
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor BOD
Reset. After these resets, the GPIF flag will continue to
be set if a mismatch is present.
Note:
Any read or write of GPIO. This will end the mis-
match condition.
Clear the flag bit GPIF.
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
IOC3
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF
interrupt flag may not get set.
R/W-0
IOC2
PIC12F683
x = Bit is unknown
R/W-0
IOC1
DS41211A-page 35
R/W-0
IOC0
bit 0
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