MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 34

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

PIC12F683
3.6.8.3
The SCS bit (OSCCON<0>) is unaffected by a Sleep
command. The clock source used after an exit from
Sleep is determined by the SCS bit.
3.6.8.4
If SCS = 0:
1.
2.
3.
If SCS = 1:
1.
2.
TABLE 3-5:
DS41211A-page 32
Address
0Ch
8Ch
8Fh
90h
2007h
Legend:
Note
The device is held in Sleep until the CPU
start-up time-out is complete.
If the primary system clock is configured as an
external oscillator (HS, XT, LP), then the OST
will be active waiting for 1024 clocks of the
primary system clock. While waiting for the OST,
the device will be held in Sleep unless
Two-speed Start-up or Fail-Safe Clock Monitor
is enabled. The OST and CPU start-up timers
run in parallel.
After both the CPU start-up and OST timers
have timed out, the device will exit Sleep and
begin instruction execution with the primary
clock defined by the F
The device is held in Sleep until the CPU
start-up time-out is complete.
After the CPU start-up timer has timed out, the
device will exit Sleep and begin instruction
execution with secondary oscillator, INTOSC.
(1)
1:
PIR1
PIE1
OSCCON
OSCTUNE
Config bits
x = unknown, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
See Register 12-1 for operation of these bits.
Name
Exiting Sleep
Sequence of Events
SUMMARY OF REGISTERS ASSOCIATED WITH OSCILLATORS
Bit 7
EEIF
EEIE
CPD
—
—
OSC
bits.
IRCF2
Bit 6
ADIF
ADIE
CP
—
CCP1IE
CCP1IF
MCLRE
IRCF1
Bit 5
—
Advance Information
PWRTE
IRCF0
TUN4
Bit 4
—
—
WDTE
OSTS
TUN3
Bit 3
CMIF
CMIE
Refer to Section 12.6.3 “Two-Speed Clock Start-up
Mode” and Section 12.6.4 “Fail-Safe Clock Moni-
tor” for details
Note:
FOSC2
OSFIF
OSFIE
TUN2
Bit 2
HTS
If a user changes SCS just before entering
Sleep mode, the system clock used when
exiting Sleep mode could be different than
the system clock used when entering
Sleep mode.
For example, if SCS = 1, the system clock
is XT, LP or HS, and the following
instructions are executed:
BCF
SLEEP
then a clock change event is executed.
The core will continue to run off INTOSC
and execute the Sleep command.
When Sleep is exited, the part will resume
operation with the primary oscillator after
the OST has expired.
TMR2IF
TMR2IE
F0SC1
TUN1
Bit 1
LTS
.
TMR1IE
TMR1IF
F0SC0
Bit 0
TUN0
SCS
 2003 Microchip Technology Inc.
OSCCON,SCS
POR, BOD
000- 0000
000- 0000
-110 x000
---0 0000
Value on:
Value on all
000- 0000
000- 0000
-110 x000
---u uuuu
Resets
other