MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 48

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

PIC12F683
6.5
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software
(Section 6.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
6.5.1
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Examples in the PICmicro
Reference Manual (DS33023) show how to read and
write Timer1 when it is running in Asynchronous mode.
TABLE 6-1:
DS41211A-page 46
0Bh/
8Bh
0Ch
0Eh
0Fh
10h
1Ah
8Ch
Legend:
Addr
Note:
INTCON
PIR1
TMR1L
TMR1H
T1CON
CMCON1
PIE1
Timer1 Operation in
Asynchronous Counter Mode
Name
are
The ANSEL (9Fh) and CMCON0 (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
needed
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
REGISTERS ASSOCIATED WITH TIMER1
T1GINV
Bit 7
EEIF
EEIE
GIE
—
to
TMR1GE
®
Bit 6
PEIE
ADIF
ADIE
Mid-Range MCU Family
—
read/write
T1CKPS1
CCP1IF
CCP1IE
Bit 5
T0IE
—
the
Advance Information
T1CKPS0
Bit 4
INTE
timer
—
—
—
T1OSCEN
Bit 3
CMIF
CMIE
GPIE
—
6.6
A crystal oscillator circuit is built-in between pins OSC1
(input) and OSC2 (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low-power oscillator rated up to 32 kHz. It will
continue to run during Sleep. It is primarily intended for
a 32 kHz crystal. Table 3-1 shows the capacitor
selection for the Timer1 oscillator.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the primary system clock is derived from the internal
oscillator. As with the system LP oscillator, the user
must provide a software time delay to ensure proper
oscillator start-up.
TRISIO5 and TRISIO4 bits are set when the Timer1
oscillator is enabled. GP5 and GP4 read as ‘0’ and
TRISIO5 and TRISIO4 bits read as ‘1’.
6.7
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To setup the timer to wake the device:
• Timer1 must be on (T1CON<0>)
• TMR1IE bit (PIE1<0>) must be set
• PEIE bit (INTCON<6>) must be set
The device will wake-up on an overflow. If the GIE bit
(INTCON<7>) is set, the device will wake-up and jump
to the Interrupt Service Routine (0004h) on an overflow.
If the GIE bit is clear, execution will continue with the
next instruction.
Note:
T1SYNC
OSFIF
OSFIE
Bit 2
T0IF
—
Timer1 Oscillator
Timer1 Operation During Sleep
The oscillator requires a start-up and
stabilization
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
TMR1CS
TMR2IE
TMR2IF
T1GSS
Bit 1
INTF
TMR1ON
CMSYNC
TMR1IF
TMR1IE
Bit 0
GPIF
 2003 Microchip Technology Inc.
time
POR, BOD
0000 0000
000- 0000
xxxx xxxx
xxxx xxxx
0000 0000
---- --10
000- 0000
before
Value on
use.
0000 0000
000- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- --10
000- 0000
Value on
all other
Resets
Thus,