MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 35

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

4.0
There are as many as six general purpose I/O pins
available. Depending on which peripherals are
enabled, some or all of the pins may not be available as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
4.1
GPIO is an 6-bit wide, bidirectional port. The
corresponding data direction register is TRISIO.
Setting a TRISIO bit (= 1) will make the corresponding
GPIO pin an input (i.e., put the corresponding output
driver in a High-impedance mode). Clearing a TRISIO
bit (= 0) will make the corresponding GPIO pin an
output (i.e., put the contents of the output latch on the
selected pin). The exception is GP3, which is input only
and its TRISIO bit will always read as ‘1’. Example 4-1
shows how to initialize GPIO.
Reading the GPIO register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. There-
fore, a write to a port implies that the port pins are read,
this value is modified and then written to the port data
latch. GP3 reads ‘0’ when MCLRE = 1.
The TRISIO register controls the direction of the
GPIO pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISIO
REGISTER 4-1:
 2003 Microchip Technology Inc.
Note:
GPIO PORTS
GPIO and the TRISIO Registers
bit 7-6:
bit 5-0:
Additional information on I/O ports may be
found in the PICmicro
ence Manual (DS33023).
GPIO — GENERAL PURPOSE I/O REGISTER (ADDRESS: 05h)
bit 7
Unimplemented: Read as ‘0’
GPIO<5:0>: GPIO I/O pin
1 = Port pin is >V
0 = Port pin is <V
Legend:
R = Readable bit
- n = Value at POR
U-0
—
®
Mid-Range Refer-
U-0
—
IH
IL
Advance Information
R/W-x
GP5
W = Writable bit
‘1’ = Bit is set
R/W-x
GP4
register are maintained set when using them as analog
inputs. I/O pins configured as analog input always read
‘0’.
EXAMPLE 4-1:
4.2
Every GPIO pin on the PIC12F683 has an interrupt-on-
change option and a weak pull-up option. GP0 has a
ultra low-power wake-up option. The next three
sections describe these functions.
4.2.1
Each of the GPIO pins, except GP3, has an individually
configurable weak internal pull-up. Control bits WPUx
enable or disable each pull-up. Refer to Register 4-3.
Each weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset by the GPPU bit
(OPTION<7>). A weak pull-up is automatically enabled
for GP3 when configured as MCLR and disabled when
GP3 is an I/O. There is no software control of the MCLR
pull-up.
BCF
CLRF
MOVLW 07h
MOVWF CMCON0
BSF
CLRF
MOVLW 0Ch
MOVWF TRISIO
BCF
Note:
Additional Pin Functions
STATUS,RP0
GPIO
STATUS,RP0
ANSEL
STATUS,RP0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-x
GP3
The ANSEL (9Fh) and CMCON0 (19h)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
WEAK PULL-UPS
INITIALIZING GPIO
R/W-x
GP2
PIC12F683
;Bank 0
;Init GPIO
;Set GP<2:0> to
;digital I/O
;Bank 1
;digital I/O
;Set GP<3:2> as inputs
;and set GP<5:4,1:0>
;as outputs
;Bank 0
x = Bit is unknown
R/W-x
GP1
DS41211A-page 33
R/W-x
GP0
bit 0