MT92210 Zarlink Semiconductor, MT92210 Datasheet - Page 45

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MT92210

Manufacturer Part Number
MT92210
Description
1023 Channel Voice Over ip (VoIP) Processor
Manufacturer
Zarlink Semiconductor
Datasheet
Data Sheet
Once written in the Packet Assembly Control & Data FIFOs, RTP packets will be read by the Assembly Copying
Process that then writes the packets into their destination buffer. The payload of RTP packets is written into the
Network Packet Buffer, while the handle to the packet is written into one of 6 destinations: one of the 4 TX Link
Packet Buffer Handles, the Network CPU Packet Buffer Handles (for internal diagnostic), or the Packet Identifier
Buffer Handles (for internal loopback).
Event indicating HDLC
packet complete
Circular Buffer
Circular Buffer
Packets (CPU-
(1 per Stream)
(1 per Bearer)
HDLC Packet Treatment Process: When an HDLC packet completes, this process will generate an event pointing to the correct TX RTP
Connection Structure, indicating that a packet should be sent to the network.
Service Indicator Process: Schedules the Assembly of RTP xxPCM packets. The service timer reads the Service Indicator Tables
synchronously with the H.100 bus and generates assembly events when enough payload is present to assemble a complete packet.
Packet Assembly: Based on assembly events, generates RTP packets and all the appropriate headers as well. Also performs silence
suppression on xxPCM data.
TX xxPCM
managed)
TX HDLC
TXCIRC5
TXCIRC4
TX CPU
entry per stream)
HDLC Stream to
LUT Structure (1
HDLC Address
TXTDM4
Table) SERVTIM1
Service Indicator
Control Memory
(1 entry per
Indicator
Process
Service
HDLC Packet
Treatment
Process
Zarlink Semiconductor Inc.
Figure 21 - Tx Flow 2
Assembly Event
channel) TXTDM5
entry per HDLC
Queue (global)
HDLC Address
global) SERVTIM0
EVENTQ0-7
Service Indicator
LUT (RTP) (1
Table (up to 16,
Structure (1 per
PCM channel)
Suppression
SILENCE0
TX Silence
TX RTP Connection
Structure (1 per
Connection)
Assembly
ASSEM0-1
Packet
Structure (1 per
TX RTP Header
Connection)
ASSEM2-5
(1 per SRC/DST
IP Address pair)
Counter Source
Identification
MT92210
45

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