MT92210 Zarlink Semiconductor, MT92210 Datasheet - Page 112

Manufacturer Part Number

MT92210

Description

1023 Channel Voice Over ip (VoIP) Processor

Manufacturer

Zarlink Semiconductor

Datasheet

1.MT92210.pdf (190 pages)

112

The TX Channel Association Memory entry points to an entry in the TX TDM Control Memory that will define either

a PCM buffer or an HDLC stream. If the entry defines a PCM buffer, it will define the compression type of the data

to be received. The MT92210 can support TDM data in PCM A-law, PCM u-law, ADPCM-40, ADPCM-32,

ADPCM-24 and ADPCM-16 formats. It can also perform auto-detection of the compression rate received using

encoded values. Lastly, the TX TDM can perform law-translation on the incoming PCM values. The data can enter

as either u-law or A-law and can also exit as either u-law or A-law, with any translation between the two.

If the TX TDM Control Memory entry defines an HDLC stream, then the entry will contain information used to

perform HDLC de-framing. Many fields are used to keep byte-per-byte context. The entry also contains fields

specifying the HDLC header format: the chip supports HDLC addresses of 0, 1 or 2 bytes, as well as 0 or 1 HDLC

control bytes. Each HDLC packet may also be trailed by a 16-bit CRC, configurable per stream. The HDLC

addresses are used to distinguish multiple channels on the same HDLC stream, with a maximum of 512 channels

per stream (using the 9 low bits of a 2-byte address), or a maximum of 256 channels when using a single-byte

address.

The TX Channel Association Memory also has an AS (Associated Stream) bit that allows greater bandwidth on

HDLC streams. When this bit is ‘1’, the TX Channel Association Memory binds 2 time slots to the corresponding TX

TDM Control Memory entry instead of 1. This increases the total capacity of the TX Data Path in HDLC mode to

2046 time slots. In this mode, the 2 time slots that are bound together are 2 adjacent H.110 streams (i.e. ct_d [0]

and ct_d [1], during the same time slot). The even stream contains the data that is logically first.

Each HDLC stream is associated to a circular buffer, of varying size depending on the maximum packet size

expected on that stream and the bandwidth of the stream. The circular buffer sizes can vary between 512 bytes and

32K bytes, in increments of 2

The format of the TX TDM Control Memory is the following:

b10

Figure 58 - Buffer Tag Format

Zarlink Semiconductor Inc.

PCM Buffer Number [9:0]

HDLC Stream Number [8:0]

LLL Buffer Number [6:0]