MT92210 Zarlink Semiconductor, MT92210 Datasheet - Page 14

• Manufacturer Part Number: MT92210
• Description: 1023 Channel Voice Over ip (VoIP) Processor
• Manufacturer: Zarlink Semiconductor

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synchronized end-to-end, allowing, for example, transparent transport of a DS3 over many IP connections
IP packet identification can be performed using any combination of IP source address, IP destination
address, UDP source port, UDP destination port and RTP Synchronization Source Identifier and are
programmable on a per-connection basis
Non-voice packets can be injected and received via the CPU Interface
Non-voice packets can be injected and received via the secondary UTOPIA port
The MT92210 can be daisy-chained to other UTOPIA devices to increase capacity
Off-the-shelf AAL5 SAR can be used to terminate data connections on a PCI bus
Support of 16 different look-up profiles, each one of which can use different fields from the packet headers
Look-up can be performed on a priority basis: for example, a packet can be looked-up using IP, UDP and
RTP headers, then the look-up result can request a second lookup using only IP and UDP headers
Binary tree of up to 128K nodes is used to route packets using packet identification key
Dynamically balanced tree system ensures optimal performance
IP, UDP and RTP header verification is performed
Multihoming is supported with any number of local IP addresses
Payload Type & Marker bit routing allows different compression formats as well as signaling packets to be
transported on the same connection
MPLS labels, MPOA tags and ELAN ID can be looked-up in binary tree to establish data format that will
follow them, logical subnet number and quality of service
Proprietary Adaptive Silence Suppression
Supported in both PCM and ADPCM formats
Built-in detection of energy level
Padding with matched-energy comfort noise
64 tone buffers used to generate tones (1 byte to 64Kb each)
32 large comfort noise buffers (16Kb to 64Kb)
Suppression indication can be generated by chip or fed externally to synchronize with off-chip compression
CODEC
Fully H.110 compatible
H.110 Master and Slave capability
Support of message channel
Low Latency Loop-back (H.110 to H.110) of 128 channels (delay <= 375 us)
Redundant Adaptive Clock Recovery Circuit
Support of 2/4/8 MHz bus speed in groups of 4 streams (8 separate groups)
Generation of H.110 compatibility signals
Dual ct_netref signals
Programmable fsync and TDM clocks for compatibility with other TDM buses
Support of plain PCM in u-law and A-law
Translation between u-law and A-law on a per connection basis
Support of ADPCM at 40, 32, 24 or 16 kbps
Dual time-slot mode allows dynamic, error-free switching between PCM and ADPCM formats with silence
suppression
Support of HDLC encapsulated mini-packets with asynchronous timing
Network Functions
Silence Suppression and Padding
H.110 Interface
TDM data formats
Zarlink Semiconductor Inc.