MT92210 Zarlink Semiconductor, MT92210 Datasheet - Page 116

• Manufacturer Part Number: MT92210
• Description: 1023 Channel Voice Over ip (VoIP) Processor
• Manufacturer: Zarlink Semiconductor

116
When an HDLC packet completes, an event must be written to the Assembly Event Queue so the packet makes it
to the network interface. Each HDLC Stream has an entry in the HDLC Stream to HDLC Address LUT Structure,
which gives, for each HDLC Stream, the list of all HDLC addresses and their corresponding TX Connection
Structures. For each Stream, the number of valid addresses is defined (anywhere from 16 to 512 in increments of
16) as well as a pointer to the corresponding HDLC Address LUT.
The format of the HDLC Stream to HDLC Address LUT Structure is the following:
In RTP, the HDLC Address LUT Structure contains a pointer to a TX Connection Structure, as well as a TI
(Timestamp Insert) bit. When this bit is ‘1’, this chip will insert its own timestamp, adding the one contained in the
HDLC packet to the final timestamp. When ‘0’, the timestamp in the HDLC packet will be used as-is.
32K Byte Buffer
512 Byte Buffer
4007FCh
4007FEh
4007FAh
4007F8h
400000h
400002h
400004h
400006h
16K Byte Buffer
256 Byte Buffer
1K Byte Buffer
8K Byte Buffer
2K Byte Buffer
4K Byte Buffer
Figure 62 - HDLC Stream to HDLC Address LUT Structure
b 15
b14
b 15
b 15
b 15
b 15
b 15
b 15
b 15
b 15
TX Circ Buffer Base [20:15]
TX Circular Buffer Base [20:14]
Figure 61 - TX Circular Buffer Base/SOP
TX Circular Buffer Base [20:13]
HDLC Address LUT Base [20:6] for HDLC Stream 510
HDLC Address LUT Base [20:6] for HDLC Stream 511
b13
HDLC Address LUT Base [20:6] for HDLC Stream 0
HDLC Address LUT Base [20:6] for HDLC Stream 1
b14
b14
b14
b14
b14
b14
b14
b14
TX Circular Buffer Base [20:12]
TX Circular Buffer Base [20:11]
b12
b13
b13
b13
b13
b13
b13
b13
b13
TX Circular Buffer Base [20:10]
TX Circular Buffer Base [20:9]
Zarlink Semiconductor Inc.
b11
b12
b12
b12
b12
b12
b12
b12
b12
TX Circular Buffer Base [20:8]
b11
b11
b11
b11
b11
b11
b11
b11
b10
b10
b10
b10
b10
b10
b10
b10
b10
b9
b9
b9
b9
b9
b9
b9
b9
b9
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b8
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b8
b8
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b7
b7
b7
b7
b7
b6
b6
b6
b6
b6
b6
b6
b6
b6
b5
SOP [14:5]
b5
b5
b5
b5
b5
b5
b5
b5
SOP [13:5]
b4
SOP [12:5]
b4
b4
b4
b4
b4
b4
b4
b4
SOP [11:5]
b3
Add Range
Add Range
Add Range
Add Range
SOP [10:5]
b3
b3
b3
b3
b3
b3
b3
b3
SOP [9:5]
b2
SOP [8:5]
b2
b2
b2
b2
b2
b2
b2
b2
SOP [7:5]
b1
b1
b1
b1
b1
b1
b1
b1
b1
b0
b0
b0
b0
b0
b0
b0
b0
b0
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