MT92210 Zarlink Semiconductor, MT92210 Datasheet - Page 103

• Manufacturer Part Number: MT92210
• Description: 1023 Channel Voice Over ip (VoIP) Processor
• Manufacturer: Zarlink Semiconductor

Data Sheet
8.4
In the other case, the RX Channel Structure Address used points to an RX HDLC Channel structure. The RX HDLC
Channel structure can do policing, report diagnostic, and indicate what type of framing to perform.
The HDLC stream number indicates to which of the 512 HDLC streams the HDLC packets obtained here belong:
this will allow a packet descriptor to be written in the queue of the correct stream. The Header Type bits indicate
what should be the form of the HDLC header inserted on the RTP packets: zero, one or two bytes of address, and
zero or one control bytes. The CRC bit indicates if a 16-bit CRC should be appended at the end of the RTP packet.
If these fields are added, their values are contained in the HDLC Address and HDLC Control Byte fields in the
control structure. Finally, the 16-bit Received Packet count and a 32-bit Received Octet Count are also present, to
allow solid diagnostics.
Before writing the HDLC RTP packet in its circular buffer, the disassembly performs all of the header, CRC and
zero-insertion functions. The MT92210 supports 2 types of HDLC framing: bit-wise and byte-wise framing (see
Annex for more details). The appropriate form of framing is applied to the entire packet (including headers and
CRC) before the packet is written in its circular buffer. When the packet is ready, the disassembly consults an
HDLC control structure that contains the base address of the circular buffer, as well as the current read and write
pointers. If there is enough room left in the circular buffer, the disassembly will write the entire packet into the buffer,
then write a packet descriptor indicating where the packet can be read and what its length is. It will also write back
the new write pointer. The RX TDM can then read the packet descriptor and send the packet onto the TDM bus.
RX HDLC channel structures also implement a policing mechanism that prevents misbehaving channels from
flooding an entire HDLC stream. This policing is implemented using a leaky bucket approach: a Maximum Bucket
Fill indicates how full the bucket may be before packets start to be discarded, and the Discharge Rate indicates
how quickly the bucket should be emptied. The bucket's fill is always positive, so in the best-case scenario the fill is
0. This ensures that, even if a connection has not received a packet for an infinite amount of time, it will not accept
an infinite size packet when it does receive one! Whenever a packet is received, the bucket is first “discharged”: this
means that the amount of time elapsed since the last received packet is calculated and is subtracted from the
Current Bucket Fill. Then, the new packet's size is added to the bucket. If the result is larger than the Maximum
Bucket Fill, the packet will be discarded, an Event Report structure will be generated containing the Policing Error
bit set, and the current packet's fill will not be added to the Current Bucket Fill. A well-configured policing
mechanism can ensure that the circular buffer never overflows.
The format of the RX RTP HDLC channel structure is the following:
HDLC Treatment
+10
+12
+14
+A
+C
+E
+0
+2
+4
+6
+8
b 15
A
Last Packet Local Time Stamp [7:0]
b14
B
HT
b13
Figure 52 - RX RTP HDLC Channel Structure
b12
0
AR
b11
Last Packet Local Time Stamp [23:8]
Received Packet Count [15:0]
Received Octet Count [31:16]
Zarlink Semiconductor Inc.
b10
Received Octet Count [15:0]
Maximum Bucket Fill [15:0]
Current Bucket Fill [15:0]
HDLC Address [15:0]
b9
0
Discharge Rate [5:0]
b8
0
RX HDLC Stream/Buffer Index [8:0]
b7
I
b6
HDLC Control [7:0]
b5
Current Bucket Fill [21:16]
b4
Header Type
b3
b2
b1
CRC
b0
MT92210
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