MT92210 Zarlink Semiconductor, MT92210 Datasheet - Page 131

• Manufacturer Part Number: MT92210
• Description: 1023 Channel Voice Over ip (VoIP) Processor
• Manufacturer: Zarlink Semiconductor

Data Sheet
10.0
The TDM interface on the MT92210 device is fully compatible with the H.110 bus and can be used to interface
either as bus master or as bus slave. It respects all of the major requirements of H.110, such as supporting up to 32
TDM streams running at 8 MHz (up to 4096 time slots), the possibility of running 16 of the streams at lower
frequencies (2 or 4 MHz), and the capability of passing 128 of the channels on H.110 in loopback.
The slave portion of the H.110 interface respects the timing requirements of this interface. It can sample the
incoming data from the ct_d pins 90 ns after the rising edge of the clock as per the spec (3/4 sampling), and it can
also sample on the falling edge (2/4 sampling) or rising edge of the clock (4/4 sampling). When driving its data, it
can tri-state its pins early (between 20 and 0 ns before the rising edge of the clock) or it can tri-state synchronously
on the rising edge of the clock. Both of these options allow flexibility in interoperation with other devices that are not
fully H.110 compliant.
10.1
When operating as a slave, the interface has the choice between clocking on A, clocking on B, clocking on A with B
as backup or clocking on B with A as backup. When set to perform automatic switchover, the interface monitors the
current bus master to see if its ct_c8 and ct_frame signals are still valid. The ct_c8 signal is checked to see if its
clock edges are within ± 35 ns of where they are supposed to be (122 ns apart). The ct_frame signal is checked to
make sure that it occurs exactly once every 1024 ct_c8 clock cycles. If either of these two errors is reported about
a given pair of bus master signals, the pair is considered invalid and the slave will switch to the backup master if
any has been programmed to do so. The MT92210 will always monitor these signals and report errors on either of
the two bus masters, even if it does not act on these errors.
10.2
When acting as a bus master, the MT92210 can choose to be a bus master on A, master on B, backup on A or
backup on B. When acting as a bus backup, the MT92210 uses the same error signals described above to
determine if the current bus master is still valid or if it should take over the bus. Note that the bus mastership can be
overridden in registers by ensuring that the chip cannot drive the H.110 clock and frame signals: this will ensure
that it remains a passive slave on the bus. If the chip is a backup on the bus and the primary master fails, it will stop
synchronizing itself on the master and track the local reference.
ct_d_out (8M,ealry Z)
ct_d_out (4M,ealry Z)
ct_d_out (2M,ealry Z)
H.110 Interface
Slave Mode
Bus Master Mode
ct_d_out (8M)
ct_d_out (4M)
ct_d_out (2M)
ct_d_in (8M)
ct_d_in (4M)
ct_d_in (2M)
ct_frame
ct_c8
63.b3
63.b3
127.b6 127.b5 127.b4 127.b3 127.b2 127.b1 127.b0
127.b6 127.b5 127.b4 127.b3 127.b2 127.b1 127.b0
31.b1
31.b1
63.b2
63.b2
Figure 74 - TDM Bus Timing - ct_d
63.b1
63.b1
Zarlink Semiconductor Inc.
31.b0
31.b0
1/2 Period Sampling
3/4 Period Sampling
4/4 Period Sampling
63.b0
63.b0
MT92210
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