MT92210 Zarlink Semiconductor, MT92210 Datasheet - Page 106

• Manufacturer Part Number: MT92210
• Description: 1023 Channel Voice Over ip (VoIP) Processor
• Manufacturer: Zarlink Semiconductor

106
8.5
The CPU manages its packets in much the same way as an HDLC stream does: it reserves a circular buffer of a
certain size and even reserves RX CPU Buffer Control Tables in much the same was HDLC streams use RX HDLC
Stream/Buffer Control Tables. All channels may write their packets into that circular buffer. Each CPU packet
received will generate an error report structure and they can be retrieved through the pointers these structures
contain. The CPU may even choose to route its packets to several different circular buffers. Finally, the CPU can
also receive an interrupt informing it that its circular buffers are getting “too full”: if any of the CPU-destined circular
buffers becomes more than half full, an interrupt can be generated. The CPU can then read the report structure
FIFO and empty all circular buffers of their packets.
The RX CPU Channel Structure also implements the same type of policing found in HDLC, for exactly the same
reasons. A misbehaving channel should not be able to flood the CPU with packets, preventing other, well-behaved
channels from getting attention. The fields in the RX CPU Channel Structure are identical to those in the RX HDLC
Channel Structure.
The format of the RX CPU Buffer Control Table is the following:
RX Circular Buffer
Base and Size
Circular Buffer Write
Pointer
Field
CPU Treatment
+0h
+2h
+4h
+6h
b 15
1FFCh
1FFEh
1000h
1008h
This field indicates the location and the size of the buffer that it used to store packets
before they are read by the software. Supported size are between 256 bytes and 64K
bytes in step of 2^k.
This pointer is used to remember the position of the next byte to be written in the circular
buffer. It thus points to an invalid byte. The pointer is defined as a pointer to bytes. This
field should be initialized to zero upon buffer creation.
b14
The RX CPU Buffer Control Table is at a fixed
address in SSRAM B. It always contains 512 entries.
b13
b12
Figure 54 - Rx CPU Buffer Control Table
Table 37 - Fields and Description
b11
RX CPU Buffer Control Structure 510
RX CPU Buffer Control Structure 511
RX CPU Buffer Control Structure 0
RX CPU Buffer Control Structure 1
Circular Buffer Read Pointer [15:0]
Circular Buffer Write Pointer [15:0]
RX Circular Buffer Base [20:8] and Size
b10
Zarlink Semiconductor Inc.
b9
b8
b7
b6
Description
b5
b4
b3
b2
b1
b0
Add