MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 7

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

MT90225/226
Data Sheet
List of Tables
Table 1 - Cell Acquisition Time..............................................................................................................................26
Table 2 - Register Summary .................................................................................................................................44
Table 3 - UTOPIA Output Link Address Registers ................................................................................................45
Table 4 - UTOPIA Output Link PHY Enable Registers..........................................................................................45
Table 5 - UTOPIA Output Control Register ...........................................................................................................46
Table 6 - UTOPIA Output User Defined Byte ........................................................................................................46
Table 7 - UTOPIA Input Link Address Registers ...................................................................................................46
Table 8 - Utopia Input Link PHY Enable Registers ...............................................................................................47
Table 9 - UTOPIA Input Control Register ..............................................................................................................47
Table 10 - UTOPIA Input Parity Error Register .....................................................................................................48
Table 11 - TX Cell RAM Control Register .............................................................................................................48
Table 12 - TX Link UTOPIA FIFO Length Definition Register ...............................................................................49
Table 13 - RX Link Control Registers....................................................................................................................50
Table 14 - Loss of Delineation Register ................................................................................................................50
Table 15 - Cell Delineation Register......................................................................................................................51
Table 16 - RX Link Select Register .......................................................................................................................51
Table 17 - RX State Register ................................................................................................................................51
Table 18 - Cell Delineation Status Register ..........................................................................................................52
Table 19 - Reset Register .....................................................................................................................................52
Table 20 - TX Link Control Registers ....................................................................................................................53
Table 21 - UTOPIA Input Cell Counter Register ...................................................................................................53
Table 22 - General Status Register .......................................................................................................................54
Table 23 - Counter Transfer Command Register ..................................................................................................54
Table 24 - IRQ Link Overflow Status Registers.....................................................................................................55
Table 25 - Counter Byte 3 Register .......................................................................................................................55
Table 26 - Counter Bytes 2 and 1 Register ...........................................................................................................56
Table 27 - Select Counter Register .......................................................................................................................56
Table 28 - IRQ Master Enable Register ................................................................................................................56
Table 29 - IRQ Link TC Overflow Enable Register................................................................................................57
Table 30 - IRQ Link Status Registers....................................................................................................................57
Table 31 - IRQ Link Enable Registers...................................................................................................................57
Table 32 - IRQ Master Status Register .................................................................................................................58
Table 33 - TDM TX Link Control Register .............................................................................................................58
Table 34 - TDM TX Mapping (timeslots 15:0) Register .........................................................................................59
Table 35 - TDM TX Mapping (timeslots 31:16) Register .......................................................................................60
Table 36 - TXCK Status Register ..........................................................................................................................60
Table 37 - RXCK Status Register..........................................................................................................................60
Table 38 - REFCK Status Register .......................................................................................................................61
Table 39 - TXSYNC Status Register .....................................................................................................................61
Table 40 - PLL Reference Control Register ..........................................................................................................61
Table 41 - TDM RX Link Control Register.............................................................................................................62
Table 42 - TDM RX Mapping (timeslots 15:0) Register.........................................................................................63
Table 43 - TDM RX Mapping (timeslots 31:16) Register.......................................................................................63
Table 44 - RXSYNC Status Register.....................................................................................................................63
Table 45 - RX Automatic ATM Synchronization Register......................................................................................63
Zarlink Semiconductor Inc.
7