MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 63

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Data Sheet
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
Bit #
Bit #
Bit #
15:0
15:0
15:8
7:0
15
14
...
1
0
Type
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Each bit controls if the corresponding time slot is used to carry ATM Traffic. When not in
use, the DSTi pin is ignored for the corresponding time slot.
This registers controls time slots 15:0.
Each bit controls if the corresponding time slot is used to carry ATM Traffic. When not in
use, the DSTi pin is ignored for the corresponding time slot.
This registers controls time slots 31:16. For T1 links, bit 8 (timeslot 24) must be zero.
RXSYNC signal faulty on link 15. Cleared by writing ’0’.
RXSYNC signal faulty on link 14. Cleared by writing ’0’.
....
RXSYNC signal faulty on link 1. Cleared by writing ’0’.
RXSYNC signal faulty on link 0. Cleared by writing ’0’.
Unused. Read 0’s.
Must write with 54 (0x36) in Bit mode cell delineation. Not used in Byte mode cell
delineation.
Table 45 - RX Automatic ATM Synchronization Register
0x0730 (1 reg)
1 reg. for all 16 RX links
0000
0x0710 - 0x071F (16 reg)
Control time slot 15:0
0000
0x0720 - 0x072F (16 reg)
Control time slot 31:16
0000
0x0741 (1 reg)
1 reg. for all RX links
0000
Table 43 - TDM RX Mapping (timeslots 31:16) Register
Table 42 - TDM RX Mapping (timeslots 15:0) Register
Table 44 - RXSYNC Status Register
Zarlink Semiconductor Inc.
Description
Description
Description
Description
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