MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 20

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

20
MT90225 Pin Description (continued)
P2,T3,Y2,AB3,
D13,D17,N23,
N25,H26,F26,
A23,D20,C16,
E2,H1,J1,M3,
D6,D10,D14,
D22,E23,F4,
K23,N4,P23,
AD12,AD15,
AC19,AD25,
AC06,AC13,
AC17,AC22,
AC14,K4,P4
AA23,AB04,
U23,AC10,
AA25,V26,
A13,A8,C5
AE6,AF8,
Pin #
AD1
C19
D19
A4
D7
A5
B6
C6
B5
C7
B4
U4
LatchClk
Name
Reset
TRST
VDD5
Test1
Test2
Test3
Test4
TMS
TDO
TCK
V3.3
V2.5
TDI
I/O
O JTAG Test Data Output. Note: TDO is tristated by TRST pin.
O Test2. Must be left not connected (NC).
O Test4. Must be left not connected (NC)
S 5 Volt supply pin. Connect to a 5 volt supply when interfacing to 5 volt
S 3.3 Volt supply pin for I/O pins. Connect to a 3.3 Volt supply.
S 2.5 Volt supply for core. Connect to a 2.5 Volt power supply.
I
I
I
I
I
I
I
I
Counter Latch Clock. The clock present at this input can be divided internally
to produce the latch signal for the internal counters. Refer to the Counter
Transfer Command register for more details. This pin has an internal
pull-down.
System Reset. This is an active low input signal. It causes the device to enter
the initial state. The Clk signal must be active to reset the internal registers.
JTAG Test Clock. TCK should be pulled down if not used.
JTAG Test Mode Select. TMS is sampled on the rising edge of TCK.
JTAG Test Data Input. This pin has an internal weak pull-down.
JTAG Test Reset (active low). Should be asserted LOW on power-up and
during reset. Must be HIGH for JTAG boundary-scan operation. This pin has
an internal weak pull-down.
Test1. Must be tied Low
Test3. Must be pulled up to V3.3 for normal operation. NOT 5V TOLERANT.
signals, otherwise, connect to a 3.3 Volt supply.
Zarlink Semiconductor Inc.
Power Signals
Description
Data Sheet