MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 47

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Data Sheet
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
15:14
Bit #
Bit #
Bit #
15
14
13
12
11
10
...
9
8
7
6
5
4
7:5
4:0
1
0
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
...
R
R
Type
R/W
R
Unused. Read all 0’s
Reserved.
Parity Bit. The incoming Parity Bit is odd parity when 0, even parity when 1.
Reserved. Write 0 for normal operation.
Reserved. Write 0 for normal operation.
UTOPIA loopback mode indicator. When set the Tx UTOPIA will accept cells and loop
these back to the Rx UTOPIA interface. The Rx UTOPIA interface will then output these
cells.
Reserved. Write 0 for normal operation.
Selects between 16- and 8-bit mode for the Utopia bus. A 0 selects a 16-bit wide bus and a
1 selects an 8-bit wide bus.
A 1 resets the state of the Input UTOPIA Controller. Write 0 for normal operation.
Reserved. Write 0 for normal operation.
Unassigned Cell Filter. A 1 signifies that the Unassigned
will be discarded. The Unassigned/Idle cell counter is incremented for each cell discarded.
Enable UTOPIA PHY address of link 15. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of link 14.A 1 enables the PHY port Address.
...
Enable UTOPIA PHY address of link 1. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of link 0.A 1 enables the PHY port Address.
Unused. Read all 0’s.
UTOPIA PHY Address of Link N.
0x0052 (1 reg)
1 register for all the UTOPIA Input ports.
000X000000000000
0x0040-0x0047 (8 reg)
0000
1 register per 2 links. Link 0 is paired with link 8, link 1 with link 9 and so on
0x0050 (1 reg)
1 register to enable the link’s input PHY address.
0000
Table 8 - Utopia Input Link PHY Enable Registers
Table 7 - UTOPIA Input Link Address Registers
Table 9 - UTOPIA Input Control Register
Zarlink Semiconductor Inc.
Description
Description
Description
a
cells coming from the ATM layer
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