MT90225AG Zarlink Semiconductor, MT90225AG Datasheet
MT90225AG
Related parts for MT90225AG
MT90225AG Summary of contents
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... I/F CTRL BUS TX Tx Utopia FIFo Processor I/F Figure 1 - MT90225/226 Functional Block Diagram 16/8 Port TC PHY Device Ordering Information MT90225AG MT90226AG - and UNI • ATM framing using cell delineation • HEC (header error control) verification & generation, error detection, and idle/unassigned cell filtering • ...
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... Provide various counters to assist in performance monitoring • Generation and insertion of Idle Cells; The Idle cells are pre-defined. • Provide structured Interrupt scheme to report various events • 16-bit microprocessor interface (adaptable to Intel or Motorola interfaces) • loopbacks 2 Zarlink Semiconductor Inc. Data Sheet ...
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... UTOPIA Operation With a Single PHY ..................................................................................................... 37 5.5 UTOPIA Operation with Multiple PHY....................................................................................................... 38 5.6 UTOPIA Loopback .................................................................................................................................... 38 5.7 Examples of UTOPIA Operation Modes ................................................................................................... 38 6.0 Support Blocks ................................................................................................................ 39 6.1 Counter Block ........................................................................................................................................... 39 6.1.1 UTOPIA Input I/F counters .............................................................................................................. 39 6.1.2 Transmit TDM I/F Counters ............................................................................................................. 40 6.1.3 Receive TDM I/F Counters .............................................................................................................. 40 6.1.4 Access to the Counters ................................................................................................................... 40 6.1.5 Latching counter mode .................................................................................................................... 40 6.2 Interrupt Block ........................................................................................................................................... 41 Table of Contents Zarlink Semiconductor Inc. 3 ...
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... Direct Access................................................................................................................................... 43 6.3.3 Indirect Access ................................................................................................................................ 43 6.3.4 Clearing of Status Bits ..................................................................................................................... 43 6.3.4.1 Toggle Bit............................................................................................................................... 43 7.0 Register Descriptions..................................................................................................... 44 7.1 Register Summary .................................................................................................................................... 44 7.2 Detailed Register Description: .................................................................................................................. 45 8.0 Application Notes ............................................................................................................ 64 8.1 Connecting the MT90225/226 to Various T1/E1/J1 Framers.................................................................... 64 9.0 AC/DC Characteristics .................................................................................................... 68 9.1 CPU Interface Timing................................................................................................................................ 73 10.0 List of Abbreviations and Acronyms ........................................................................... 83 11.0 ATM Glossary................................................................................................................. 84 4 Table of Contents Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 23 - CPU Interface Intel Timing - Read Access ........................................................................................ 75 Figure 24 - CPU Interface Motorola Timing - Write Access ................................................................................. 76 Figure 25 - CPU Interface Intel Timing - Write Access......................................................................................... 77 Figure 26 - ST-BUS Timing .................................................................................................................................. 79 Figure 27 - Generic Bus Timing ........................................................................................................................... 80 Figure 28 - JTAG Port Timing .............................................................................................................................. 81 Figure 29 - System Clock and Reset.................................................................................................................... 82 List of Figures Zarlink Semiconductor Inc. MT90225/226 5 ...
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... Zarlink Semiconductor Inc. Data Sheet ...
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... Table 38 - REFCK Status Register .......................................................................................................................61 Table 39 - TXSYNC Status Register .....................................................................................................................61 Table 40 - PLL Reference Control Register ..........................................................................................................61 Table 41 - TDM RX Link Control Register.............................................................................................................62 Table 42 - TDM RX Mapping (timeslots 15:0) Register.........................................................................................63 Table 43 - TDM RX Mapping (timeslots 31:16) Register.......................................................................................63 Table 44 - RXSYNC Status Register.....................................................................................................................63 Table Automatic ATM Synchronization Register......................................................................................63 List of Tables Zarlink Semiconductor Inc. MT90225/226 7 ...
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... Zarlink Semiconductor Inc. Data Sheet ...
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... PD TXCKio VSS VSS VSS VSS up_r/w up_a[9] up_a[5] up_a[2] VDD5 up_d[13 [2] [0] or up_wr Figure 2 - MT90226 Pinout (Bottom View) Zarlink Semiconductor Inc VDD5 PD NC TMS Reset TDI ...
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... TXSyn TXCKio VSS VSS VSS VSS up_r/w up_a[9] up_a[5] up_a[2] VDD5 [2] cio[1] [0] or up_wr Figure 3 - MT90225 Pinout (Bottom View) Zarlink Semiconductor Inc. Data Sheet VDD5 PD NC TMS Reset ...
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... URxData and URxSOC MT90226 outputs. In this case, URxData and URxSOC would be enabled only in cycles following those with URxEnb asserted. In UTOPIA L1, URxEnb must not be tied low and must transition from high (disabled) to low (enabled) to indicate the beginning of data transfer. Zarlink Semiconductor Inc. 11 ...
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... MT90226 accepts the signals on its processor bus. MT90226 signals to the processor that an interrupt condition is pending inside the MT90226. TDM Interface Signals output is set to high impedance for unused time slots and if the link is not used aligned with TXCKio and TxSYNCio. Zarlink Semiconductor Inc. Data Sheet ...
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... TDM Interface Receive Clock. This input line represents the clock for the receive serial TDM data. The expected frequency value to be received at this input clock is defined by the user through the RX Link TDM Control register. These pins have internal weak pull-downs. Zarlink Semiconductor Inc. 13 ...
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... JTAG Test Reset (active low). Should be asserted LOW on power-up and during reset. Must be HIGH for JTAG boundary-scan operation. This pin has an internal weak pull-down. Test1. Must be tied Low Test3. Must be pulled up to V3.3 for normal operation. NOT 5V TOLERANT. Power Signals signals, otherwise, connect to a 3.3 Volt supply. Zarlink Semiconductor Inc. Data Sheet ...
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... MT90226 Pin Description (continued) Pin # Name I/O AB23,AC4, VSS S Ground. AC5,AC23, AD3,AD24, AE2,AE25,B2, B25,C3,C24, D4,D5,D23,E4, L11,L12,L13, L14,L15,L16, M11,M12,M13, M14,M15,M16, N11,N12,N13, N14,N15,N16, P11,P12,P13,P 14,P15,P16, R11,R12,R13, R14,R15,R16, T11,T12,T13, T14,T15,T16 IC I AC16,AE16, AF16,AC15, AE15,AF15, AD14,AE14 AF13, AF14 Description Internal Connection. Must be grounded externally. Zarlink Semiconductor Inc. 15 ...
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... A19,B19 D16, A17 R26, T24 V23, Y25, AB25, AE22, AF20, AE18, R25, U26, W26, Y24, AB24, AC21, AD19, AF18 B7,A7,D8,C8, B8,D9,C9,B9 16 Description Not Connected. Pull-down. Connect to VSS via a high value resistor e.g. 10kohm. Don’t tie to VSS directly. Zarlink Semiconductor Inc. Data Sheet ...
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... URxData and URxSOC MT90225 outputs. In this case, URxData and URxSOC would be enabled only in cycles following those with URxEnb asserted. In UTOPIA L1, URxEnb must not be tied low and must transition from high (disabled) to low (enabled) to indicate the beginning of data transfer. Zarlink Semiconductor Inc. 17 ...
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... MT90225 accepts the signals on its processor bus. MT90225 signals to the processor that an interrupt condition is pending inside the MT90225. TDM Interface Signals The output is set to high impedance for unused time slots and if the link is not used aligned with TXCKio and TXSYNCio. Zarlink Semiconductor Inc. Data Sheet ...
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... Input Reference Clock inputs Receive the de-jittered transmit clock reference to be internally routed to the TXCKio transmit clocks. These pins have internal weak pull-downs. System Signals System Clock (50 MHz nominal). In the MT90225, this clock is used for all internal operations of the device. Zarlink Semiconductor Inc. 19 ...
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... JTAG Test Reset (active low). Should be asserted LOW on power-up and during reset. Must be HIGH for JTAG boundary-scan operation. This pin has an internal weak pull-down. Test1. Must be tied Low Test3. Must be pulled up to V3.3 for normal operation. NOT 5V TOLERANT. Power Signals signals, otherwise, connect to a 3.3 Volt supply. Zarlink Semiconductor Inc. Data Sheet ...
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... L23,E25,C25, B26,D24,C15, A6,A3,C4, B3,A2 A9,C10,B10, A10,C11,D11, B11,A11,C12, D12,B12,A12, C13,B13,A14, B14,C14,A15, B15 D15, A16, B16 B17,C17,A18, B18,D18,C18, A19,B19 D16, A17 B7,A7,D8,C8, PD B8,D9,C9,B9 Description Internal Connection. Must be grounded externally. Not Connected. Pull-down. Connect to VSS via a high value resistor e.g. 10kohm. Don’t tie to VSS directly. Zarlink Semiconductor Inc. 21 ...
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... T1/E1/J1 framers, SHDSL modems or other low speed link devices. Each of these serial links can be assigned link. The MT90225 supports serial links, while the MT90226 supports serial links. The functional block diagram at Figure 4 illustrates the transmit function of the MT90225. 22 Zarlink Semiconductor Inc. Data Sheet ...
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... Cell_in_control Figure 4 - MT90225/226 Functional Block Diagram -Transmitter Transmitter Cell RAM TX Link Utopia FIFO 0 TX Link Utopia FIFO 1 Output Controller and Idle Cell Insertion TX Link Utopia FIFO 14 TX Link Utopia FIFO 15 Zarlink Semiconductor Inc. Serial Streams Link 0 P/S P/S Link 1 Link 14 P/S Link 15 P/S 23 ...
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... Refer to Description of the TDM interface in Section 4.0 for more details scramble the ATM cell payload field. The MT90225/226 ATM cell payload + used to generate the HEC field of the ATM cell. By default, the ATM Zarlink Semiconductor Inc. Data Sheet ...
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... Idle Cell Cell Removal Idle Cell Cell Removal Cell Idle Cell Removal System Clock Valid HEC (byte by byte) Incorrect HEC (cell by cell) HUNT ALPHA DELTA Consecutive SYNC Figure 6 - Cell Delineation State Diagram Zarlink Semiconductor Inc. UTOPIA Interface PRESYNC Correct HEC (cell by cell) 25 ...
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... Table 1 - Cell Acquisition Time ATM CELL DELINEATION SYNC STATE HCS Multi-Bit Error Detected (cell discarded) HCS Single Bit Error Detected (corrected or dropped) No HCS Errors Detected Figure 7 - SYNC State Block Diagram Zarlink Semiconductor Inc. Data Sheet ALPHA Cell Consecutive Discarded Incorrect HCS’s ...
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... High Impedance mode for that time slot. The TDM TX link is independent of the TDM RX link and can have different mapping (using different time slots and optionally a different number of time slots). + 1). The use of the polynomial can be disabled by writing to bit the RX Zarlink Semiconductor Inc. 27 ...
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... This enables a direct interface to existing framers and opens up the option to interface to generic nx64 devices. Fractional T1/E1 is supported as well by selecting the time slots that are used to carry ATM traffic. 28 bit 193 bit 1 Unused or Bit Cell High Impedance Figure 8 - Single mode - Generic 1.544 MHz Zarlink Semiconductor Inc. Data Sheet ... bit 2 ... Bit Cell ... ... ... ...
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... Note: Frame pulse polarity and clock edge are fixed in ST-BUS mode. Channel 0 bit 7 Channel 0 bit 0 ... ... Bit Cell ... ... ... ... Figure 9 - Single mode - Generic 2.048 MHz ... Channel 0 bit 7 Channel 0 bit 0 ... Bit Cell ... ... Figure 10 - Single mode - ST-BUS Zarlink Semiconductor Inc. ... Channel 1 bit 7 ... Bit Cell Bit Cell ... ... ... ... Channel 1 bit 7 ... Bit Cell Bit Cell ... ... 29 ...
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... Note that all four links in a group must have the same settings. Data rate (bits 6: Multiplex mode (bits 4: Clock and Sync format (bit Enable (bit Cell delineation mode (bit 10 of TDM RX Link Control only Zarlink Semiconductor Inc. Data Sheet ...
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... Link Control registers for those three links must be set. The four links operate using the Clock and SYNC signal of link 0. The same logic applies for the other groups example of this grouped multiplexing, the MT90225/226 supports four high speed links on links and 12. Zarlink Semiconductor Inc. 31 ...
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... TXCK and TCSYNC are programmed as inputs, TXSYNC must be de-asserted, and the transmitter will be "free running" and will output serial data continuously. If the TXSYNC is defined as output, a frame pulse is generated for every 512 TXCK cycles, but can be ignored. The same logic applies for the other pairs. 32 Zarlink Semiconductor Inc. Data Sheet ...
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... To use remote loopback, TXCK and TXSYNC must be configured as output sourcing from the RXCK and RXSYNC of the same port. The loopback per link basis with the limitation that physical links are paired: i.e. TX link 0 is connected to RX link 0 and so on. Zarlink Semiconductor Inc. 33 ...
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... When TXCK and TXSYNC are outputs, TXCK source is software selectable and can be any of the RXCK signals or four external REFCK inputs (see Figure 11). The TXSYNC is generated from the TXCK signal. The RXCK pins are always defined as inputs and the proper signal must be provided to each input. 34 Zarlink Semiconductor Inc. Data Sheet ...
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... A value of ’0’ for these bits means that activity was observed on this clock. This circuitry does not measure the frequency of a clock signal, it only detects activity on the TXCK, RXCK and REFCK signals. Cell Delineation TX Cell FIFO Zarlink Semiconductor Inc. DSTi RXCK S/P ...
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... The ’00’ option is used to always accept a cell from the ATM layer. The HEC is verified and if wrong, the UTOPIA Input counter associated with the UTOPIA port for cells with bad HEC is incremented. The MT90225/226 will re-generate a valid HEC based on the content of the 4-byte header that was received. 36 Zarlink Semiconductor Inc. Data Sheet ...
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... A single ATM layer device with a UTOPIA L2 MPHY port can be connected to the ATM input port of one MT90225/226. Another ATM-Layer device using the UTOPIA L2 MPHY input interface is used to receive ATM cells from the MT90225/226. The address pins should be set to the value programmed by the management interface. Zarlink Semiconductor Inc. 37 ...
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... ATM Layer 38 , the Tx UTOPIA port will accept cells and loop these back to the Rx UTOPIA Physical Layer TxClk TxEnb* TxAddr TxClav TxData TxSOC . . ATM MT90225/226 . Rxclk . RxEnb* . RxAddr RxClav RxData RxSOC Figure 12 - ATM Interface to MT90225/226 Zarlink Semiconductor Inc. Data Sheet Framer Framer ...
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... HEC, removed or not but not including the cells where the HEC is corrected Physical Layer Txclk TxEnb* TxAddr TxClav TxData TxSOC MT90225/226 Rxclk RxEnb* RxAddr RxClav RxData RxSOC Txclk TxEnb* TxAddr TxClav TxData TxSOC MT90225/226 Rxclk RxEnb* RxAddr RxClav RxData RxSOC Zarlink Semiconductor Inc. Framer . . Framer Framer . . Framer 39 ...
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... After each latch signal, the counters are reset order to report the number of events between two latch commands. Before the latching mode is enabled, the counters may be loaded (or reset), but the software should not write to the counters after the latching mode is enabled. 40 Zarlink Semiconductor Inc. Data Sheet ...
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... Link 2 Link 1 Link IRQ A Link T Registers U S Link 15 0 LCD End of LCD 9 Figure 14 - IRQ Register Hierarchy Zarlink Semiconductor Inc IRQ Master Registers IRQ PIN S E Link 0 41 ...
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... UTOPIA RX FIFO. The 10 interrupt sources are organized as follows: • 1 bit (12) for the RX UTOPIA FIFO overflow • 4 bits (11:8) for the UTOPIA Input counters • 2 bits (7,5) for the TX TDM Link counters • 3 bits (3:1) for the RX TDM Link counters 42 Zarlink Semiconductor Inc. Data Sheet ...
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... Typically, this bit is toggled 2.5 system clock cycles after performing the write action. To use the toggle bit, its state (either must be read (polled) and its state is changed (toggled) when a write command is completed. This bit is particularly useful when the processor clock is much faster than the MT90225/226 system clock. Zarlink Semiconductor Inc. 43 ...
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... Counter Bytes 2 and 1 Register Sync Select Counter Register 0000 IRQ Master Enable Register 0000 IRQ Link TC Overflow Enable Register 0000 IRQ Link Status Registers 0000 IRQ Link Enable Registers 0000 IRQ Master Status Register Table 2 - Register Summary Zarlink Semiconductor Inc. Data Sheet Description ...
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... TXSYNC Status Register 0000 PLL Reference Control Register 0000 TDM RX Link Control Register 0000 TDM RX Mapping (timeslots 15:0) Register 0000 TDM RX Mapping (timeslots 31:16) Register 0000 RXSYNC Status Register 0000 RX Automatic ATM Synchronization Register Table 2 - Register Summary (continued) Description Description Zarlink Semiconductor Inc. Description 45 ...
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... Link 0 is paired with link 8, link 1 with link 9 and so on Reset Value (Hex): 0000 Bit # Type 15:13 R Unused. Read all 0’s. 12:8 R/W UTOPIA PHY Address of Link N+8. Table 7 - UTOPIA Input Link Address Registers 46 Description Description Description Zarlink Semiconductor Inc. Data Sheet ...
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... Reserved. Write 0 for normal operation. 4 R/W Unassigned Cell Filter signifies that the Unassigned will be discarded. The Unassigned/Idle cell counter is incremented for each cell discarded. Description Description Description Table 9 - UTOPIA Input Control Register Zarlink Semiconductor Inc. a cells coming from the ATM layer 47 ...
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... Bit # Type 15:8 R Unused. Read all 0’ Status Bit. Goes to 0 during initialization and returns completion of initialization. 48 Description b cells coming from the ATM layer will be discarded. Description Description Table Cell RAM Control Register Zarlink Semiconductor Inc. Data Sheet ...
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... Bit # Type 15:12 R Unused. Read 0’s. 11:8 R/W TX UTOPIA FIFO Length for Link N+8. 7:4 R/W Reserved. Write 0’s for normal operation. 3:0 R/W TX UTOPIA FIFO Length for Link N. Table Link UTOPIA FIFO Length Definition Register Description Table Cell RAM Control Register Description Zarlink Semiconductor Inc. 49 ...
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... The value of this register is multiplied by 2 before being loaded in the internal counter. (The internal counter value can be from 2 to 510). Note that a value not allowed as an LCD condition would be generated. 50 Description Table Link Control Registers Description Table 14 - Loss of Delineation Register Zarlink Semiconductor Inc. Data Sheet ...
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... The value is updated on completion of the write action in the RX Link Select register Reset Value (Hex): 0000 Bit # Type 15:6 R Unused. Read all 0’s. 5:4 R Reserved. 3:2 R Reserved. 1:0 R Cell Delineation State: 00: Hunt 01: Presync 10: Sync. 11: Reserved. Description Table 15 - Cell Delineation Register Description Table Link Select Register Description Table State Register Zarlink Semiconductor Inc. 51 ...
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... Write reset the receiver 6 R/W Write reset the transmitter 5 R/W Write reset counters 4:3 R/W Write 00 for normal operation. 2:0 R/W Reserved. Write 0 for normal operation. 52 Description (1 reg) Description means no action means no action Write 0 for normal operation. Table 19 - Reset Register Zarlink Semiconductor Inc. Data Sheet ...
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... Count total Cells for Link 1. 1: Count only User Cells for Link 1. 0 R/W 0: Count total Cells for Link 0. 1: Count only User Cells for Link 0. Table 21 - UTOPIA Input Cell Counter Register Description Table Link Control Registers Description Zarlink Semiconductor Inc. 53 ...
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... R/W 00: Initialize all the counters with 0. 01: Initiate a read or write of the counter value. 10: Initiate a read or write of the IRQ enable counter bit. 11: Unused. Table 23 - Counter Transfer Command Register 54 Description Table 22 - General Status Register Description Zarlink Semiconductor Inc. Data Sheet ...
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... Reset Value (Hex): 0000 Bit # Type 15:8 R Unused. Read all 0’s. 7:0 R/W A read accesses the MSB (byte #3) of the Counter selected in the Select Counter register. A write will hold the value to be written to the selected counter. Description Description Table 25 - Counter Byte 3 Register Zarlink Semiconductor Inc. 55 ...
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... IRQ pin is low if the corresponding bit in the IRQ Master Register is set. A’0’ means that the IRQ level is not affected by the corresponding bit. 56 Description Description Table 27 - Select Counter Register Description Table 28 - IRQ Master Enable Register Zarlink Semiconductor Inc. Data Sheet ...
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... Unused. Read all 0’s. 11:0 R/W Each bit set to ’1’ will enable the generation of the interrupt when the corresponding bit in the IRQ Link Status register is set. Description Description Table 30 - IRQ Link Status Registers Description Table 31 - IRQ Link Enable Registers Zarlink Semiconductor Inc. 57 ...
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... Valid only for ST-BUS mode. 58 Description Table 32 - IRQ Master Status Register Description 00001: RXCK1 00011: RXCK3 00101: RXCK5 00111: RXCK7 01001: RXCK9 01011: RXCK11 01101: RXCK13 01111: RXCK15 10001: REFCK1 10011: REFCK3 Table 33 - TDM TX Link Control Register Zarlink Semiconductor Inc. Data Sheet ...
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... Type 15:0 R/W Each bit controls if the corresponding time slot is used to carry ATM Traffic. When not in use, the DSTo pin is in High Z mode for the corresponding time slot. This registers controls time slots 15:0. Table 34 - TDM TX Mapping (timeslots 15:0) Register Description Description Zarlink Semiconductor Inc. 59 ...
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... Bit # Type 15 R When 1: RXCK faulty on link 15 When 1: RXCK faulty on link 14. ... R .... 1 R When 1: RXCK faulty on link When 1: RXCK faulty on link 0. 60 Description Description Table 36 - TXCK Status Register Description Table 37 - RXCK Status Register Zarlink Semiconductor Inc. Data Sheet ...
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... RXCK6 01110: RXCK14 10110: RXSYNC6 11110: RXSYNC14 00111: RXCK7 01111: RXCK15 10111: RXSYNC7 11111: RXSYNC15 Table 40 - PLL Reference Control Register Description Table 38 - REFCK Status Register Description Table 39 - TXSYNC Status Register Description 10000: RXSYNC0 11000: RXSYNC8 10001: RXSYNC1 11001: RXSYNC9 Zarlink Semiconductor Inc. 61 ...
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... When 1, the data is sampled at the falling edge of RXCK. This bit is ignored in ST-BUS Format. 0 R/W Sync polarity: When 0, the sync pulse is active low. When 1, the sync pulse is active high. This bit is ignored in ST-BUS Format. 62 Description Table 41 - TDM RX Link Control Register Zarlink Semiconductor Inc. Data Sheet ...
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... RX links Reset Value (Hex): 0000 Bit # Type 15:8 R Unused. Read 0’s. 7:0 R/W Must write with 54 (0x36) in Bit mode cell delineation. Not used in Byte mode cell delineation. Table Automatic ATM Synchronization Register Description Description Description Table 44 - RXSYNC Status Register Description Zarlink Semiconductor Inc. 63 ...
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... Data Lines ST-BUS I/F DATA ST-BUS I/F DATA 4.096 MHz 8 kHz ST-BUS I/FCLOCKS Dejittered TX CLK to Framers (1.544 or 2.048 MHz) MT9042 Functions Zarlink Semiconductor Inc. Data Sheet Zarlink MT9076B Legacy Trunks Framer/LIU at 1 Mbps Zarlink MT9076B Legacy Trunks Framer/LIU at 1 Mbps Zarlink MT9076B ...
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... TXSYNC[15] DSTo[15] Note: All MT9076B devices are configured in Line Sync. mode Figure 16 - MT90225 interfacing MT9076 ST-BUS mode with asynchronous links. (each link has synchronous Tx and Rx clocks) MT9076B DSTo C4b F0b DSTi MT9076B DSTo C4b F0b DSTi Zarlink Semiconductor Inc. 20 MHz +/-50 PPM 65 ...
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... MHz 8 kHz [R7] TDM Data 1.544 or 2.048 MHz 8 kHz [T7] 1.544 or 2.048 MHz 8 kHz [R7] External Source MT9076B in IMA mode. MT9042 PLL is optional. TxCK[i] is sourced from RxCK[i] or REFCK[j] Zarlink Semiconductor Inc. Data Sheet MT9076B #1 DSTi DSTo C4 Legacy Trunks Mbps ExCLK RxFP MT9076B #2 ...
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... Note: The MT9072 is configured in IMA mode. (asynchronous links with independent Rx and Tx clocks) TXCKio[0] TXSYNCio[0] DSTo[0] DSTi[0] RXSYNCi[0] RXCKi[0] TXCKio[15] TXSYNCio[15] DSTo[15] DSTi[15] RXSYNCi[15] RXCKi[15] Figure 18 - MT90225 interfacing MT9072 Zarlink Semiconductor Inc. CKi[0] TPOS[0] FP[0] TNEG[0] DSTi[0] T2o[0] To LIU DSTo[0] RxBF[0] RPOS[0] RxDLC[0] RNEG[0] E2i[0] MT9072 #1 ...
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... DD2.5 I 29/ 133/ DD3 2.0 5 -0.5 0 115 222 ILPD I - 4.6 I5V Zarlink Semiconductor Inc. Data Sheet Min Max -0.3 3.1 2.5 -0.3 3.9 3.3 -1.0 6.5 -1.0 3.9 -1.0 6 -40 125 ST ‡ Max Units Test Conditions 85 °C 2.63 V 3.46 5.25 Test Conditions mA System Clock 52 MHz. TDM clock @ 2 ...
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... 0 4.6 O5V Zarlink Semiconductor Inc. Test Conditions mA Source V =2 Source V =2 Source V =0 Source V =0 For 5V tolerant outputs For all other outputs ...
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... Output hold from RxClk tT9 Signal going low impedance to RxClk tT10 Signal going high impedance to RxClk tT11 Signal going low impedance from RxClk tT12 Signal going high impedance from RxClk Zarlink Semiconductor Inc. Data Sheet 1 Min Max 0 50 MHz 40% 60 ...
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... Output delay from RxClk tT8 Output hold from RxClk tT9 Signal going low impedance to RxClk tT10 Signal going high impedance to RxClk tT11 Signal going low impedance from RxClk tT12 Signal going high impedance from RxClk Zarlink Semiconductor Inc. Min. Max MHz 40% 60 ...
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... Figure 19 - Setup and Hold Time Definition Signal Valid Signal Going High Impedance tT12 Signal Going High Impedance From Clock Figure 20 - Tri-State Timing t clk_min Signal Valid Figure 21 - Output Delay Timing would be equivalent to tT5 or tT7 for the device IS Zarlink Semiconductor Inc. Data Sheet t 1 T10 ...
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... UP_R/W or UP_CS signal. In Intel timing mode, the data is clocked into MT90225/226 pre-load register on the rising edge of the UP_R/W or UP_CS signal. Right after that transition, the data is transferred to the MT90225/226’s internal register. Writing data into this register can take up 2 system clock cycles. Zarlink Semiconductor Inc. 73 ...
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... UP_R/W UP_AD[11:0] UP_D[15:0] Figure 22 - CPU Interface Motorola Timing - Read Access 74 Sym Min Typ Max ACC Address Valid t li Data Valid t acc Zarlink Semiconductor Inc. Data Sheet Units Test Conditions ...
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... UP_CS t ws UP_R/W UP_AD[11:0] UP_D[15:0] Figure 23 - CPU Interface Intel Timing - Read Access Sym Min Typ Max ACC Address Valid t li Data Valid t acc Zarlink Semiconductor Inc. Units Test Conditions ...
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... Figure 24 - CPU Interface Motorola Timing - Write Access 76 Sym Min Typ Max ADH CSH (see Note Address Valid Data Valid t su Zarlink Semiconductor Inc. Data Sheet Units Test Conditions cycle system clock t csh t adh ...
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... Figure 25 - CPU Interface Intel Timing - Write Access Sym Min Typ Max ADH t 1 CSH (see Note 1) t adh ADDRESS VALID t su DATA VALID Zarlink Semiconductor Inc. Units Test Conditions cycle system clock t csh ...
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... Min Max Units Sym Typ t 5 SIS t 10 SIH t 25 SOD ODE Zarlink Semiconductor Inc. Data Sheet Units Notes ns Max width is one clock ns period =150pF Test Conditions ns ...
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... Mb/s mode, last channel = ch 127. t FPW FPH t t SIS SIH Bit 7, Channel 0 Bit 6, Channel 0 t SOD Bit 7, Channel 0 Bit 6, Channel 0 Figure 26 - ST-BUS Timing Zarlink Semiconductor Inc IH(min IL(max Bit 5, Channel Bit 5, Channel 0 CT ...
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... FPW SIS SIH Bit 7, Channel 0 Bit 6, Channel 0 t SOD Bit 7, Channel 0 Bit 6, Channel 0 t FOD Figure 27 - Generic Bus Timing Zarlink Semiconductor Inc. Data Sheet IH(min IL(max Bit 5, Channel Bit 5, Channel 0 CT ...
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... DIH t 2 MSSU t 5 MSH t DOD t 15 TRST t 2 RST t msh t dih t disu t dod Figure 28 - JTAG Port Timing Zarlink Semiconductor Inc. Max Units Test Conditions ns BSDL spec’s 12 MHz MCLK cycles t tclk t t tclkl ...
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... CLK t 10 CLKL t 10 CLKH t CLKR t CLKF t 10 RST t t clkr clkf t rst Figure 29 - System Clock and Reset Zarlink Semiconductor Inc. Data Sheet Max Units Test Conditions 20 ns for full operation of TDM Ring, could be longer ns ns 1.2 ns 1.2 ns clk period t clk t t clkl ...
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... Physical Medium Dependent QoS Quality of Service RAI Remote Alarm Indication RDI Remote Defect Indication RFI Remote Failure Indication SAR Segmentation and Reassembly SOC Start of Cell TC Transmission Convergence UTOPIA Universal Test and Operations Physical Interface for ATM UNI User Network Interface Zarlink Semiconductor Inc. 83 ...
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... Multi-Vendor Integration Protocol (MVIP) - MVIP standards are designed to support the inter-operability of prod- ucts from different manufacturers and the portability of computer software between products from different manu- facturers with the goal of facilitating new and improved applications of computer and communications equipment. 84 Zarlink Semiconductor Inc. Data Sheet ...
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... ATM cells. Also Virtual Circuit. Glossary References: The ATM Glossary - ATM Year 97 - Version 2.1, March 1997 The ATM Forum Glossary - May 1997 ATM and Networking Glossary (http://www.techguide.com/comm/index.html) Mitel Semiconductor Glossary of Telecommunications Terms - May 1995. Zarlink Semiconductor Inc. 85 ...
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... Zarlink Semiconductor Inc. Data Sheet ...
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... Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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