MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 11

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Data Sheet
MT90226 Pin Description
H3,H4,G1,G2,
T1,R3,R4,R2,
R1,P3,P1,N1,
N2,N3,M2,M4
G3,G4,F1,F2,
U2,U1,T4,T2,
F3,E1,E3,D1,
D2,C1,D3,C2
Y4,W3,W4,
W2,W1
Pin #
U3
V1
V4
V3
V2
H2
K3
K2
J4
UTxSOC
URxData
URxSOC
UTxData
UTxAddr
UTxClav
URxEnb
UTxEnb
URxPar
UTxPar
UTxClk
URxClk
Name
[15:0]
[15:0]
[4:0]
ATM Output Port Signals (UTOPIA Receive Interface)
ATM Input Port Signals (UTOPIA Transmit Interface)
I/O
O UTOPIA Transmit Cell Available Signal. For cell-level flow control in a
O UTOPIA Receive Data Bus. 16 (or 8) bit wide data driven from MT90226 to
O UTOPIA Receive Parity. Odd (or Even) Parity bit generated by the MT90226
O UTOPIA Receive Start of Cell Signal. Active high asserted by the MT90226
I
I
I
I
I
I
I
I
UTOPIA Transmit Data Bus. 16 (or 8) bit wide data driven from ATM LAYER
device to MT90226. Bit 15 (or 7) is the MSB. All arriving data between the last
word (byte) of the previous cell and the first word (byte) of the following cell
(indicated by the SOC signal) is ignored. UTxData[15:8] have internal weak
pull-downs.
UTOPIA Transmit Parity. Odd (or Even) Parity bit generated by the ATM
LAYER. The parity bit is sampled on the rising edge of UTxClk. UTxPar has an
internal weak pull-down.
UTOPIA Transmit Start of Cell Signal. Active HIGH signal asserted by the
ATM LAYER device when TxData[15:0] ([7:0]) contains the first valid word
(byte) of the cell. After this signal is high, the following 26 word (52 bytes)
should contain valid data. The MT90226 waits for another TxSOC and TxEnb
signal after reading a complete cell.
UTOPIA Transmit Clock. Transfer clock from the ATM Layer device to the
MT90226 which synchronizes data transfers on TxData[15:0] ([7:0]). This
signal is the clock of the incoming data. Data is sampled on the rising edge of
this signal.
UTOPIA Transmit Data Enable. Active LOW signal asserted by the ATM
LAYER device during cycles when TxData contains valid cell data.
MPHY environment, TxClav is an active high tri-stateable signal from the
MT90226 to the ATM LAYER device.
Transmit Address.Five bit wide address bus driven by the ATM layer device
to poll and select the appropriate PHY address. TxAddr[4] is the MSB.
ATM layer device. RxData[15] ([7]) is the MSB. To support multiple PHY
configurations, RxData is driven only when RxEnb and port is selected. It is
tri-stated otherwise.
to the ATM Layer.
when RxData contains the first valid word (byte) of a cell.
UTOPIA Receive Clock
the PHY layer. Data changes after the rising edge of this signal.
UTOPIA Receive Data Enable. Active LOW signal asserted by the ATM layer
device to indicate that URxData[15:0] ([7:0]) and URxSOC will be sampled at
the end of the next cycle. In multiple PHY configurations, URxEnb is used to
tri-state URxData and URxSOC MT90226 outputs. In this case, URxData and
URxSOC would be enabled only in cycles following those with URxEnb
asserted. In UTOPIA L1, URxEnb must not be tied low and must transition
from high (disabled) to low (enabled) to indicate the beginning of data transfer.
Zarlink Semiconductor Inc.
.
This signal is the clock driven from the ATM layer to
Description
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