MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 49

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Data Sheet
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Bin):
15:12
Bit #
Bit #
11:8
7:4
3:0
4:1
6
5
0
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Write 1 to this bit for normal operation. Write 0 in conjunction with bit 0 to initialize the TX
Cell RAM;
Reserved. Write 0 for normal operation.
Reserved. Write 0’s for normal operation.
Write 0 to initialize the internal Cell RAM.
Unused. Read 0’s.
TX UTOPIA FIFO Length for Link N+8.
Reserved. Write 0’s for normal operation.
TX UTOPIA FIFO Length for Link N.
Table 12 - TX Link UTOPIA FIFO Length Definition Register
1 register per 2 links. Link 0 is paired with link 8, link 1 is paired with link 9 and so
0x008B-0x0092 (8 reg)
0101
on.
0x0080 (1 reg)
Used for initialization of the internal TX Internal Cell RAM (Idle Cell)
000000001X000000
Table 11 - TX Cell RAM Control Register
Zarlink Semiconductor Inc.
Description
Description
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