MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 23

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Data Sheet
2.1 Cell In Control
In general terms, the MT90225/226 transmit input port has the following properties:
•
•
•
•
•
•
•
•
•
•
•
•
The input port can be enabled to remove (filter) Unassigned or Idle cells. If Unassigned or Idle Cell Filtering is
enabled, the device checks for and discards Unassigned or Idle cells. This function is programmed in the UTOPIA
Input Control (0x0052) register.
Section 5.0 describes the UTOPIA Interface in more detail.
cell level handshaking complies with the ATM Forum UTOPIA L1 and L2 Specification
behaves like a UTOPIA MPHY Device or Single PHY Device
each port can be enabled or disabled independently
parity (odd or even) can be checked
optionally verifies and then generates the HEC for incoming cells
includes the ATM Forum polynomial when generating the HEC (default option that can be disabled)
either passes or removes incoming Idle cells
either passes or removes incoming Unassigned cells
provides a counter per UTOPIA port for the total number of Idle/Unassigned/Filler cells with a valid HEC or
optionally the total number of User cells (24 bits/16 bit latched)
provides a counter per UTOPIA port for the total number of cells with wrong incoming HEC (24 bits/16 bit
latched)
provides a counter per UTOPIA port for the total number of cells handled (24 bits/16 bit latched)
provides counters for Parity errors
ATM In
Cell_in_control
UTOPIA L2
Interface
and
Figure 4 - MT90225/226 Functional Block Diagram -Transmitter
TX Link Utopia FIFO 14
TX Link Utopia FIFO 15
TX Link Utopia FIFO 0
TX Link Utopia FIFO 1
Transmitter
Cell RAM
Zarlink Semiconductor Inc.
Controller
Insertion
Idle Cell
Output
and
P/S
P/S
P/S
P/S
Streams
Link 14
Link 15
Serial
Link 0
Link 1
23