MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 22

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

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1.0 Device Architecture
The MT90225/226 implements Transmission Convergence layer functions.
The primary function of MT90225/6 is to transfer the cells from the UTOPIA Interface to a serial (TDM) port and from
TDM ports to UTOPIA interface without any overhead. Up to 16 UTOPIA PHY addresses can be supported - one
per serial port. A different UTOPIA PHY address is assigned to each one of the links.
1.1 MT90225/6 Main Functions
The MT90225/226 circuitry implements the following functions:
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The MT90225/226 can be separated into four major independent blocks and three support blocks.The four major
independent blocks are:
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The three support blocks are:
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2.0 The ATM Transmit Path
The transmit path corresponds to a cell flow from the ATM Layer towards the PHY Layer. The ATM cell path on the
transmit side starts at the UTOPIA L2 or L1 Interface. Once ATM cells are received at the UTOPIA port, the device
transfers these cells to the transmit block.
The MT90225/226 provides ATM cell mapping and transmission convergence blocks to transport ATM cells over a
maximum of sixteen flexible serial interface ports. These serial interface ports communicate with most off-the-shelf
T1/E1/J1 framers, SHDSL modems or other low speed link devices.
Each of these serial links can be assigned to a TC link. The MT90225 supports up to 16 serial links, while the
MT90226 supports up to 8 serial links.
The functional block diagram at Figure 4 illustrates the transmit function of the MT90225.
Utopia Level 1 or 2 PHY Interface
Incoming HEC verification and correction (optional),
Generation of a new HEC byte
Format outgoing bytes into multi-vendor TDM formats
Retrieve ATM Cells from the incoming multi-vendor TDM format
Perform cell delineation
Provide various counters to assist in performance monitoring
Generation and insertion of Idle Cells; The Idle cells are pre-defined.
Provide structured Interrupt scheme to report various events
16-bit microprocessor interface (adaptable to Intel or Motorola interfaces)
loopbacks
the ATM Transmit Path
the ATM Receive Path
the TDM Interface
the UTOPIA Interface
the Counter Block
the Interrupt Block
the Microprocessor Interface Block
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