MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 48

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

48
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Bin):
Bit #
Bit #
Bit #
11:0
15:8
1:0
15
14
13
13
12
a. Unassigned Cells have a fixed header corresponding to 00000000 00000000 00000000 0000xxx0.
b. Idle Cells have a fixed header corresponding to 00000000 00000000 00000000 00000001
3
2
7
Type
Type
Type
ROL
ROL
R/W
R/W
R/W
R/W
W
R
R
R
R
Idle Cell Filter. A 1 signifies that the Idle
The Unassigned/Idle cell counter is incremented for each cell discarded.
ATM Forum Polynomial. A 1 disables the addition of the ATM Forum Polynomial calculation
on the HEC calculated as per I.432. A 0 means that the coset value is included in the HEC
value.
HEC Verification.
11: Enable HEC error correction if 1 bit is wrong, discard cell if more than 1 bit are wrong.
10: Discard cell if HEC is wrong, no HEC correction.
01: Enable HEC error correction if 1 bit is wrong, no correction if more than 1 bit wrong, cell
is not discarded if HEC is wrong.
00: No verification of HEC.
Unused. Read all 0’s.
Status Bit. Goes to 0 during initialization and returns to 1 on completion of initialization.
Indicates that the parity error counter has rolled-over. This is a sticky bit which is set by
the hardware and reset by the user (by writing ’0’ to this bit).
Indicates that at least one parity error has occurred since this register was reset. This is a
sticky bit which is set by the hardware and reset by the user (by writing ’0’ to this bit.
When written with a 1 the internal TX UTOPIA Parity Error Counter value will be
transferred to the lower 12 bits of this register. When written with ’0’, no transfer is done.
Reading a 1 in this register indicates that the transfer to bits 11:0 has completed. Reading
a 0 indicates that the transfer is not completed yet.
When this bit is set the TX UTOPIA Parity Error Counter will be reset. When this bit is
reset the TX UTOPIA Parity Error Counter will operate normally.
TX UTOPIA Parity Error Counter. These bits contain the value of the TX UTOPIA Parity
Error Counter. The counter must be loaded into the register using bit 13.
0x0052 (1 reg)
1 register for all the UTOPIA Input ports.
000X000000000000
0x0053 (1 reg)
1 register to contain information about parity errors on the Tx UTOPIA data bus.
0000
0x0080 (1 reg)
Used for initialization of the internal TX Internal Cell RAM (Idle Cell)
000000001X000000
Table 9 - UTOPIA Input Control Register (continued)
Table 10 - UTOPIA Input Parity Error Register
Table 11 - TX Cell RAM Control Register
Zarlink Semiconductor Inc.
Description
Description
b
Description
cells coming from the ATM layer will be discarded.
Data Sheet