MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 27

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

MT90225/226
Data Sheet
After correction (when enabled), the resulting ATM cell is passed to the Rx Link UTOPIA FIFO.
If a single or multi bit error occurs, the state machine transitions to the ’detection’ state. When a cell with a good
HEC is detected, the state machine returns to the ’correction’ state. The HEC calculation normally includes the ATM
6
4
2
FORUM polynomial (X
+ X
+ X
+ 1). The use of the polynomial can be disabled by writing to bit 1 or 9 of the RX
Link Control (0x00C0-0x00C7) register.
3.1.1 Cell Delineation with Sync signal
When a serial TDM stream is used with a sync signal such as a TDM Frame Pulse, byte alignment is guaranteed.
As a result, the hunt algorithm searches for the cell boundary based on a predefined number of bytes. If it fails, the
hunt algorithm shifts one byte and tries again.
3.1.2 Cell Delineation without Sync signal
When a serial TDM stream is used without a sync signal (e.g. in non-framed mode), byte alignment is not
guaranteed. The hunt algorithm searches for the cell boundary based on a predefined number of bytes. If it fails,
the hunt algorithm shifts one bit and tries again. When the hunt algorithm succeeds, it will have determined both the
cell boundary and the byte alignment. This mode of operation is selected by setting bit 10 of TDM RX Link Control
(0x0700-0x070F) register.
3.2 De-Scrambling and ATM Cell Filtering
The CD circuit can de-scramble the cell payload field. The de-scrambling algorithm can be enabled or disabled using
bit 5 or 13 of the RX Link Control (0x00C0-0x00C7) registers.
The MT90225/226 can be programmed, using the RX Link Control (0x00C0-0x00C7) registers, to discard received
ATM cells with HEC errors using bits 2 and 10.
HEC error correction is optional and can be enabled by the CPU. When the option to correct an incoming HEC value
with 1 bit error is selected, the HEC is corrected and the cell is not counted as a cell with a bad HEC. If the option
to remove the cells that are received with a bad HEC is selected, then the incoming cells are discarded. The counter
is not incremented if the HEC value is corrected, when the option is enabled.
Incoming Idle and Unassigned cells can be detected and dropped automatically.
4.0 Description of the TDM Interface
The Transmit TDM blocks are independent of the Receive TDM blocks. The TX port of a framer can be connected
to any of the MT90225/226 TX UTOPIA Input ports and the RX port of a framer can be connected to any of the
MT90225/226 RX UTOPIA Output ports.
The TDM interface provides a variety of modes to work with different T1/E1/DSL framers for various applications.
In general, there are four major modes: Single mode, Wire-OR mode, Multiplex mode and Non-framed mode. Each
mode can be further divided into several minor modes.
4.1 Single mode
In this mode, all links are active and can be used. Its minor modes of operation include Generic 1.544MHz mode
(F-bit and 24 time slots), Generic 2.048MHz mode (32 time slots), and ST-BUS mode (32 time slots).
Mapping registers are used to determine when a time slot is used to carry the ATM traffic. There are two 16-bit
mapping registers for each TDM TX and for each TDM RX links. Each bit of the 2 registers (total of 32 bits) controls
one time slot. A bit value of 1 corresponds to an active time slot. A value of 0 corresponds to an inactive time slot
and the output is in High Impedance mode for that time slot. The TDM TX link is independent of the TDM RX link
and can have different mapping (using different time slots and optionally a different number of time slots).
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