MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 31

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Data Sheet
4.3 Multiplex mode
A multiplex mode is offered by many multi-channel T1/E1 framers to multiplex several T1/E1 links on to one high
speed data link. The same mode is available on MT90225/226, where two or four 2.048 Mb/s links are multiplexed
using a common clock of 8.192 or 16.384 MHz. In this major mode, two or four links running at 2.048 bps (either
2.048MHz Single mode or 4.096MHz Single mode) are interleaved on a time slot basis (byte by byte) to provide a
multiplexed link at a data rate of 4.096 Mb/s or 8.192 Mb/s.
In Multiplex mode, links are treated or processed the same way as they are in Single mode. The only difference is
the way that data is carried on TDM bus. In Single mode, each link uses its own TDM port to carry data, whereas in
Multiplex mode two or four links shares a single high speed port. As in Wire-OR mode, links in Multiplex mode must
be configured in the same as they were in Single mode, except for TDM Link Control registers.
When multiplexed mode is used, the time slots on the multiplexed links have to use a common synchronized clock
source and Frame Pulse for the multiplexed links. Multiplexing of fractional T1/E1 is also possible through the control
of merged mapping registers.
Only ST-BUS mode is supported in Multiplex mode.
There are two minor modes in Multiplex mode, 2-link multiplexing and 4-link multiplexing.
4.3.1 Multiplex mode - 2 link multiplexing
In this mode, two links of 2.048 Mb/s are multiplexed onto a single link of 4.096 Mb/s. The links that are paired are
pre-determined: link 0 is multiplexed with link 1, link 2 is multiplexed with link 3 and so on. When link 0 and link 1
are multiplexed, the pins associated with link 1 cannot be used and are tri-stated, however, bit 7 of its TDM TX(RX)
Link Control registers must be set. The two links operate using the Clock and SYNC signals of link 0. The same
logic applies for the other groups.
As an example of this grouped multiplexing, the MT90225/226 support eight high speed links on links 0, 2, 4, 6, 8
10, 12 and 14.
Unlike Single mode, the only clock format supported is ST-BUS mode. The data rate is 4.096 Mb/s. A clock of 8.192
MHz is used and the Frame pulse indicates the first bit of the first time slot of a frame of 64 time slots. The mapping
registers of the 2 physical links are merged by bit-to-bit interleaving to form a larger mapping register supporting up
to 64 time slots.
This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by
the following settings. Note that both links in a pair must have the same settings.
4.3.2 Multiplex mode - 4 link multiplexing
In this mode, four links of 2.048 Mb/s are multiplexed onto a single link of 8.192 Mb/s. The links that are combined
are pre-determined: links 0, 1, 2 and 3 are grouped and the multiplexed input/output is available on link 0. When link
0 is used, the pins associated with links 1, 2 and 3 cannot be used and are tri-stated, however, bit 7 of TDM TX(RX)
Link Control registers for those three links must be set. The four links operate using the Clock and SYNC signal of
link 0. The same logic applies for the other groups.
As an example of this grouped multiplexing, the MT90225/226 supports four high speed links on links 0, 4, 8 and 12.
Data rate (bits 6:5) = 10
Multiplex mode (bits 4:3) = 01
Clock and Sync format (bit 2) = 1
Enable (bit 7) = 1
Cell delineation mode (bit 10 of TDM RX Link Control only) = 0
TX clock direction (bit 9 of TDM TX Link Control only) = 1
Zarlink Semiconductor Inc.
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