MT58L256L32D Micron Semiconductor Products, Inc., MT58L256L32D Datasheet - Page 7

• Manufacturer Part Number: MT58L256L32D
• Description: 8Mb Syncburst SRAM, 3.3V Vdd, 3.3V I/O, Pipelined, Dcd,
• Manufacturer: Micron Semiconductor Products, Inc.

TQFP PIN DESCRIPTIONS
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
MT58L512L18D_D.p65 – Rev. 2/02
92
43
32-35, 44-50, 32-35, 44-50,
(S Version)
80-82, 99,
(T Version)
(S Version)
x18
100
37
36
93
94
87
88
89
98
92
64
97
86
83
–
–
92
43
(S Version)
81, 82, 99,
x32/x36
(T Version)
(S Version)
100
37
36
93
94
95
96
87
88
89
98
92
64
97
86
83
SYMBOL
BWa#
BWb#
BWd#
BWE#
BWc#
ADV#
GW#
CE2#
OE#
SA0
SA1
CLK
CE#
CE2
SA
ZZ
TYPE
Input Synchronous Byte Write Enables: These active LOW inputs allow
Input Byte Write Enable: This active LOW input permits BYTE WRITE
Input Synchronous Address Inputs: These inputs are registered and
Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit
Input Clock: This signal registers the address, data, chip enable, byte write
Input Synchronous Chip Enable: This active LOW input is used to enable
Input Synchronous Chip Enable: This active LOW input is used to enable
Input Snooze Enable: This active HIGH, asynchronous input causes the
Input Synchronous Chip Enable: This active HIGH input is used to enable
Input Output Enable: This active LOW, asynchronous input enables the
Input Synchronous Address Advance: This active LOW input is used to
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
(continued on next page)
must meet the setup and hold times around the rising edge of
CLK. Two different pinouts are available for the TQFP package.
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
operations and must meet the setup and hold times around the
rising edge of CLK.
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
enables and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
the device and is sampled only when a new external address is
loaded. CE2# is only available on the S Version.
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
the device and is sampled only when a new external address is
loaded.
data I/O output drivers.
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on this pin effectively causes
wait states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
7
8Mb: 512K x 18, 256K x 32/36
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DESCRIPTION
©2002, Micron Technology, Inc.