MT58L256L32D Micron Semiconductor Products, Inc., MT58L256L32D Datasheet - Page 3

• Manufacturer Part Number: MT58L256L32D
• Description: 8Mb Syncburst SRAM, 3.3V Vdd, 3.3V I/O, Pipelined, Dcd,
• Manufacturer: Micron Semiconductor Products, Inc.

GENERAL DESCRIPTION (continued)
clock (CLK) and snooze enable (ZZ). There is also a burst
mode input (MODE) that selects between interleaved
and linear burst modes. The data-out (Q), enabled by
OE#, is also asynchronous. WRITE cycles can be from
one to two bytes wide (x18) or from one to four bytes wide
(x32/x36), as controlled by the write control inputs.
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be in-
ternally generated as controlled by the burst advance
input (ADV#).
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes to
be written. During WRITE cycles on the x18 device, BWa#
controls DQa pins and DQPa; BWb# controls DQb pins
and DQPb. During WRITE cycles on the x32 and x36
devices, BWa# controls DQa pins and DQPa; BWb# con-
trols DQb pins and DQPb; BWc# controls DQc pins and
DQPc; BWd# controls DQd pins and DQPd. GW# LOW
causes all bytes to be written. Parity bits are only avail-
able on the x18 and x36 versions.
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
MT58L512L18D_D.p65 – Rev. 2/02
Asynchronous inputs include the output enable (OE#),
Burst operation can be initiated with either address
Address and write control are registered on-chip to
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
3
able register which delays turning off the output buffer
an additional cycle when a deselect is executed. This
feature allows depth expansion without penalizing sys-
tem performance.
V
compatible. The device is ideally suited for Pentium
and PowerPC pipelined systems and systems that benefit
from a very wide, high-speed data bus. The device is also
ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide
applications.
sramds) for the latest data sheet.
TQFP PINOUTS
two pinouts in the industry. Micron will support both
pinouts for this part.
DD
This device incorporates an additional pipelined en-
Micron’s 8Mb SyncBurst SRAMs operate from a +3.3V
Please refer to Micron’s Web site
At the time of the writing of this data sheet, there are
power supply, and all inputs and outputs are TTL-
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(www.micron.com/
©2002, Micron Technology, Inc.
®