MT58L128L32D1 Micron Semiconductor Products, Inc., MT58L128L32D1 Datasheet - Page 23

• Manufacturer Part Number: MT58L128L32D1
• Description: 4Mb Syncburst SRAM, 3.3V Vdd, 3.3V I/O, Pipelined, Dcd,
• Manufacturer: Micron Semiconductor Products, Inc.

WRITE TIMING PARAMETERS
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1_F.p65 – Rev. F, 1/03 EN
BWa#-BWd#
SYMBOL
t
f
t
t
t
t
t
t
t
KC
KF
KH
KL
KQ
KQLZ
OELZ
OEHZ
AS
ADDRESS
(NOTE 4)
(NOTE 2)
ADSC#
ADSP#
BWE#,
ADV#
OE#
CLK
CE#
D
Q
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
6. Timing is shown assuming that the device was not enabled before entering into this sequence.
is HIGH, CE2# is HIGH and CE2 is LOW.
MIN
6.0
2.3
2.3
1.5
A1
0
0
High-Z
High-Z
-6
t ADSS
MAX
t CES
166
3.5
3.5
t AS
A2
Back-to-Back READs
t ADSH
t CEH
t KH
t AH
t KC
t KQLZ
MIN
(NOTE 5)
7.5
2.5
2.5
1.5
Q(A1)
0
0
t KL
-7.5
t KQ
MAX
133
4.0
4.2
Q(A2)
t OEHZ
MIN
3.0
3.0
1.5
2.0
10
0
-10
t WS
Single WRITE
MAX
t DS
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
D(A3)
100
READ/WRITE TIMING
5.0
4.5
A3
t DH
t WH
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
A4
23
t OELZ
SYMBOL
t
t
t
t
t
t
t
t
t
ADSS
WS
DS
CES
AH
ADSH
WH
DH
CEH
4Mb: 256K x 18, 128K x 32/36
(NOTE 1)
Q(A4)
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MIN
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
BURST READ
Q(A4+1)
-6
MAX
Q(A4+2)
MIN
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
-7.5
MAX
Q(A4+3)
DON’T CARE
MIN
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
©2003, Micron Technology, Inc.
D(A5)
-10
A5
Back-to-Back
MAX
WRITEs
UNDEFINED
D(A6)
UNITS
A6
ns
ns
ns
ns
ns
ns
ns
ns
ns