MT58L128L32D1 Micron Semiconductor Products, Inc., MT58L128L32D1 Datasheet
MT58L128L32D1
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MT58L128L32D1 Summary of contents
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... Contact factory for more information. 4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM MT58L256L18D1_F.p65 – Rev. F, 1/03 EN PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 4Mb: 256K x 18, 128K x 32/36 3.3V I/O PIPELINED, DCD SYNCBURST SRAM ™ MT58L256L18D1, MT58L128L32D1, MT58L128L36D1 3. Cycle Deselect ) DD ...
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ADDRESS SA0, SA1, SA REGISTER MODE ADV# CLK ADSC# ADSP# BYTE “b” WRITE REGISTER BWb# BYTE “a” WRITE REGISTER BWa# BWE# GW# ENABLE CE# REGISTER CE2 CE2# OE# 18 ADDRESS SA0, SA1, SA REGISTER MODE ADV# CLK ADSC# ADSP# ...
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GENERAL DESCRIPTION (continued) Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also ...
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TQFP PIN ASSIGNMENT TABLE PIN # x18 x32/x36 PIN # 1 NC NC/DQPc DQc DQc DQc DQc 32 ...
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ADV# 83 ADSP# 84 ADSC# 85 OE# 86 BWE# 87 GW# 88 CLK CE2# 92 BWa# 93 BWb CE2 97 CE ...
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TQFP PIN DESCRIPTIONS x18 x32/x36 SYMBOL 32–35, 44–50, 32–35, 44–50, 80–82, 99, 81, 82, 99, 100 100 93 93 BWa BWb# – 95 BWc# – 96 BWd BWE GW# 89 ...
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TQFP PIN DESCRIPTIONS (continued) x18 x32/x36 ADSP ADSC MODE (a) 58, 59, (a) 52, 53, DQa 62, 63, 68, 69, 56–59, 62, 63 72, ...
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CE# BWb# NC CE2# BWE CE2 NC BWa# CLK GW ...
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FBGA PIN DESCRIPTIONS x18 x32/x36 SYMBOL 2A, 2B, 3P, 2A, 2B, 3P, 3R, 4P, 4R, 3R, 4P, 4R, 8P, 8R, 9P, 9R, 8P, 8R, 9P, 10A, 10B, 10P, 9R, 10A, 10B, 10R, 11A, 11R 10P, 10R, ...
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FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 9B 9B ADSP ADSC MODE (LB0#) (a) 10J, 10K, (a) 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11G 11K, 11L, 11M (b) 1J, 1K, (b) 10D, ...
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FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 2H, 4C, 4N, 5C, 2H, 4C, 4N, 5C, 5D, 5E 5F, 5D, 5E 5F, 5G, 5H, 5J, 5G, 5H, 5J, 5K, 5L, 5M, 5K, 5L, 5M, 6C, 6D, 6E, 6F, 6C, 6D, 6E, ...
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INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) X...X00 X...X01 X...X10 X...X11 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) X...X00 X...X01 X...X10 X...X11 PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18) FUNCTION READ READ ...
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TRUTH TABLE OPERATION ADDRESS DESELECTE Cycle, Power-Down DESELECTE Cycle, Power-Down DESELECTE Cycle, Power-Down DESELECTE Cycle, Power-Down DESELECTE Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply DD Relative to V .................................... -0.5V to +4.6V SS Voltage Supply DD Relative to V .................................... -0.5V to +4. ...................................................... -0. Storage Temperature (plastic) ........... ...
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TQFP CAPACITANCE DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance FBGA CAPACITANCE DESCRIPTION Address/Control Input Capacitance Output Capacitance (Q) Clock Capacitance NOTE: 1. This parameter is sampled. 2. Preliminary package data. 4Mb: 256K x 18, 128K x ...
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I OPERATING CONDITIONS AND MAXIMUM LIMITS DD (0°C ≤ T ≤ +70° +3.3V +0.3V/-0.165V unless otherwise noted DESCRIPTION Device selected; All inputs ≤ V Power Supply or ≥ V Current: Operating V ...
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TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance Test conditions follow standard test methods (Junction to Ambient) Thermal Resistance (Junction to Top of Case) FBGA THERMAL RESISTANCE DESCRIPTION Junction to Ambient Test conditions follow standard test methods (Airflow of 1m/s) Junction to ...
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) (0°C ≤ T ≤ +70° DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to ...
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AC TEST CONDITIONS Input pulse levels ................. V ................... V Input rise and fall times .................................... 1ns Input timing reference levels ..................... V Output reference levels ........................... V Output load ........................... See Figures 1 and 2 LOAD DERATING CURVES Micron ...
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SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced The duration of SNOOZE MODE dictated by the length of time ...
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KC CLK ADSS t ADSH ADSP# ADSC ADDRESS GW#, BWE#, BWa#-BWd# t CES t CEH CE# (NOTE 2) ADV# OE# (NOTE 3) t KQLZ Q ...
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KC CLK ADSS t ADSH ADSP# t ADSS ADSC ADDRESS A1 Byte write signals are ignored for first cycle when ADSP# initiates burst. BWE#, BWa#-BWd# GW# t CES t CEH ...
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KC CLK ADSS t ADSH ADSP# ADSC ADDRESS BWE#, BWa#-BWd# (NOTE 4) t CES t CEH CE# (NOTE 2) ADV# OE High-Z t KQLZ Q ...
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TYP +0.06 0.32 -0.10 PIN #1 ID NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per ...
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BALL A11 165X Ø 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.40 7.50 ±0.05 15.00 ±0.10 7.00 ±0.05 NOTE: 1. All dimensions in millimeters MAX or typical where noted. DATA SHEET ...
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REVISION HISTORY Updated package drawings ................................................................................................................................... January 9/03 Removed "Preliminary Package Data" from front page .............................................................................. February 22/02 Removed 119-pin PBGA package and references ........................................................................................ February 14/02 Removed note "Not Recommended for New Designs," Rev. 6/01 ...................................................................... June 7/01 Added ...