MT58L128L32D1 Micron Semiconductor Products, Inc., MT58L128L32D1 Datasheet - Page 18

• Manufacturer Part Number: MT58L128L32D1
• Description: 4Mb Syncburst SRAM, 3.3V Vdd, 3.3V I/O, Pipelined, Dcd,
• Manufacturer: Micron Semiconductor Products, Inc.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (0°C ≤ T
NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1_F.p65 – Rev. F, 1/03 EN
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
Write signals
(BWa#-BWd#, BWE#, GW#)
Data-in
Chip enables (CE#, CE2#, CE2)
Hold Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
Write signals
(BWa#-BWd#, BWE#, GW#)
Data-in
Chip enables (CE#, CE2#, CE2)
2. Measured as HIGH above V
3. This parameter is measured with the output loading shown in Figure 2 unless otherwise noted.
4. This parameter is sampled.
5. Transition is measured ±500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough
7. OE# is a “Don’t Care” when a byte write enable is sampled LOW.
8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
discussion on these parameters.
A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the required setup
and hold times.
when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold
times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
A
≤ +70°C; V
DD
, V
IH
DD
and LOW below V
Q = +3.3V +0.3V/-0.165V unless otherwise noted)
SYMBOL
t
t
t
t
t
t
t
t
KQHZ
OEHZ
ADSH
t
KQLZ
OELZ
ADSS
t
t
t
t
t
t
KQX
OEQ
AAH
t
AAS
t
t
t
f
t
t
t
WH
CEH
CES
KQ
WS
AH
DH
KC
KH
KF
KL
AS
DS
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
MIN
6.0
2.3
2.3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
IL
0
0
.
-6
18
MAX
166
3.5
3.5
3.5
3.5
4Mb: 256K x 18, 128K x 32/36
MIN
7.5
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0
0
-7.5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MAX
133
4.0
4.2
4.2
4.2
MIN
3.0
3.0
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
10
0
-10
MAX
100
5.0
5.0
5.0
4.5
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
©2003, Micron Technology, Inc.
3, 4, 5, 6
3, 4, 5, 6
3, 4, 5, 6
3, 4, 5, 6
NOTES
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
2
2
3
7