MT57W1MH18J Micron Semiconductor Products, Inc., MT57W1MH18J Datasheet - Page 5

• Manufacturer Part Number: MT57W1MH18J
• Description: 18Mb Ddrii SRAM, 1.8V Vdd, Hstl, 4-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

NOTE:
18Mb: 1.8V V
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
1. In this approach, the second clock pair drives the C and C# clocks but is delayed such that return data meets setup
2. Consult Micron Technical Notes for more thorough discussions of clocking schemes.
3. Data capture is possible using only one of the two signals. CQ and CQ# clocks are optional use outputs.
4. For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended
and hold times at the bus master.
over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs.
DD
MASTER
, HSTL, DDRIIb4 SRAM
ASIC)
(CPU
BUS
or
SRAM 1 Input CQ#
SRAM 2 Input CQ#
SRAM 1 Input CQ
SRAM 2 Input CQ
Cycle Start#
Delayed K#
Delayed K
Source K#
Source K
Address
R/W#
DQ
R
Figure 3: Application Example
R = 50Ω
DQ
SA
LD#
Vt = V
SRAM 1
R/W#
REF
C C#
K
5
CQ#
CQ
ZQ
K#
2 MEG
R = 250Ω
1.8V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
8, 1 MEG
DD
DQ
SA
, HSTL, DDRIIb4 SRAM
R
LD#
SRAM 2
Vt
Vt
R/W#
C C#
X
18, 512K
K
CQ#
ZQ
CQ
K#
R = 250Ω
©2003 Micron Technology, Inc.
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