MT57W1MH18J Micron Semiconductor Products, Inc., MT57W1MH18J Datasheet - Page 12

• Manufacturer Part Number: MT57W1MH18J
• Description: 18Mb Ddrii SRAM, 1.8V Vdd, Hstl, 4-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Table 7:
Notes 1–6
Table 8:
Notes 7, 8
NOTE:
18Mb: 1.8V V
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. ­means rising edge; ¯ means falling edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges except if C
3. R/W# and LD# must meet setup and hold times around the rising edge (LOW to HIGH) of K and are registered at the
4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification. A0 + 1 refers to the address input during a WRITE or
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential, but permits most rapid restart by
7. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation
8. This table illustrates operation for x18 devices. The x36 device operation is similar, except for the addition of BW2#
OPERATION
OPERATION
WRITE Cycle:
Load address, input write data on
two consecutive K and K# rising
edges
READ Cycle:
Load address, read data on two
consecutive C and C# rising edges
NOP: No operation
STANDBY: Clock stopped
WRITE D0:17 at K rising edge
WRITE D0:17 at K# rising edge
WRITE D0:8 at K rising edge
WRITE D0:8 at K# rising edge
WRITE D9:17 at K rising edge
WRITE D9:17 at K# rising edge
WRITE nothing at K rising edge
WRITE nothing at K# rising edge
and C# are HIGH, then data outputs are delivered at K and K# rising edges.
rising edge of K.
READ cycle. A0 + 2 refers to the next internal burst address in accordance with the burst sequence.
overcoming transmission line charging symmetrically.
provided that the setup and hold requirements are satisfied.
(controls DQ18:DQ26) and BW3# (controls DQ27:DQ35). The x8 device operation is similar, except that NW0# con-
trols DQ0:DQ3, and NW1# controls DQ4:DQ7.
DD
, HSTL, DDRIIb4 SRAM
Truth Table
BYTE WRITE Operation
LD#
H
X
L
L
R/W#
H
X
X
L
Stopped
L®H
L®H
L®H
K
12
2 MEG
Q
Previous
D
High-Z
OUT
C#(t)­
1.8V V
K(t)­
State
IN
DQ
at
at
(A0)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(A0)
X
L®H
L®H
L®H
L®H
K
Q
8, 1 MEG
DD
D
K#(t + 1)­
OUT
C(t + 1)­
Previous
IN
High-Z
State
(A0 + 1)
, HSTL, DDRIIb4 SRAM
DQ
(A0 + 1)
at
at
L®H
L®H
L®H
L®H
K#
Q
D
X
OUT
C#(t + 2)­
K(t + 2)­
Previous
IN
High-Z
State
18, 512K
(A0 + 2)
DQ
(A0 + 2)
at
at
BW0#
0
0
0
0
1
1
1
1
©2003 Micron Technology, Inc.
Q
D
K#(t + 3)­
OUT
C(t + 3)­
Previous
IN
High-Z
State
(A0 + 3)
X
BW1#
DQ
(A0 + 3)
at
at
0
0
1
1
0
0
1
1
36