MT57W1MH18J Micron Semiconductor Products, Inc., MT57W1MH18J Datasheet - Page 2

• Manufacturer Part Number: MT57W1MH18J
• Description: 18Mb Ddrii SRAM, 1.8V Vdd, Hstl, 4-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

to the output data clocks C and C#, eliminating the
need for separately capturing data from each individ-
ual DDR SRAM in the system design.
enhance pipelined WRITE cycles and reduce READ-to-
WRITE turnaround time. WRITE cycles are self-timed.
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 1.8V I/O levels to shift data
during this testing mode of operation.
ing an appropriate reference voltage (V
device is ideally suited for applications requiring very
rapid data transfer by operation in data-doubled
mode. The device is also ideal in applications requiring
the cost benefits of pipelined CMOS SRAMs and the
reduced READ-to-WRITE turnaround times of Late
Write SRAMs.
all inputs and outputs are HSTL-compatible. The
device is ideally suited for cache, network, telecom,
DSP , and other applications that benefit from a very
wide, high-speed data bus.
sramds) for the latest data sheet.
DDR Operation
tion through high clock frequencies (achieved through
pipelining) and double data rate mode of operation. At
slower frequencies, the DDR SRAM requires a single
no-operation (NOP) cycle when transitioning from a
READ to a WRITE cycle. At higher frequencies, a sec-
ond NOP cycle may be required to prevent bus conten-
tion. NOP cycles are not required when switching from
a WRITE to a READ.
18Mb: 1.8V V
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
Additional write registers are incorporated to
Four balls are used to implement JTAG test capabili-
The device can be used in HSTL systems by supply-
The SRAM operates from a 1.8V power supply, and
Please refer to Micron’s Web site
The DDR SRAM enables high performance opera-
DD
, HSTL, DDRIIb4 SRAM
(www.micron.com/
REF
). The
2
2 MEG
data for the write are stored in registers. The write
information must be stored because the SRAM cannot
perform the last word write to the array without con-
flicting with the read. The data stays in this register
until the next WRITE cycle occurs. On the first WRITE
cycle after the READ(s), the stored data from the earlier
WRITE will be written into the SRAM array. This is
called a posted write.
if that address was written in the previous cycle. Dur-
ing this READ cycle, the SRAM array is bypassed, and
data is read instead from the data register storing the
recently written data. This is transparent to the user.
This feature facilitates system data coherency.
cessor, the Claymore DDR SRAM. Single data rate
operation is not supported, hence, no SD/DD# ball is
provided. Only bursts of four are supported. The need
for echo clocks is reduced or eliminated by the two sin-
gle-ended input clocks (C and C#), although tightly
controlled echo clocks (CQ and CQ#) are provided. The
SRAM synchronizes its output data to these data clock
rising edges, if provided. No differential clocks are used
in this device. This clocking scheme provides greater
system tuning capability than Claymore SRAMs and
reduces the number of input clocks required by the
bus master.
PARTIAL WRITE Operations
x8 devices in which nibble write is supported. The
active LOW write controls, BWx# (NWx#), are regis-
tered coincident with their corresponding data. This
feature can eliminate the need for some READ-MOD-
IFY-WRITE cycles, collapsing it to a single BYTE/NIB-
BLE WRITE operation in some instances.
If a READ occurs after a WRITE cycle, address and
A read can be made immediately to an address even
The DDR SRAM differs in some ways from its prede-
BYTE WRITE operations are supported, except for
1.8V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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8, 1 MEG
DD
, HSTL, DDRIIb4 SRAM
X
18, 512K
©2003 Micron Technology, Inc.
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