MT57W1MH18J Micron Semiconductor Products, Inc., MT57W1MH18J Datasheet - Page 19

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MT57W1MH18J

Manufacturer Part Number
MT57W1MH18J
Description
18Mb Ddrii SRAM, 1.8V Vdd, Hstl, 4-Word Burst,
Manufacturer
Micron Semiconductor Products, Inc.
Datasheet
NOTE:
18Mb: 1.8V V
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
R/W#
CQ#
1. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e.,
2. Outputs are disabled (High-Z) one clock cycle after a NOP.
3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be
CQ
LD#
C#
DQ
K#
C
K
A
t KHCH
A0 + 1.
required to prevent bus contention.
Qx2
NOP
1
t KHKL
t
IVKH
DD
, HSTL, DDRIIb4 SRAM
t KLKH
t AVKH t KHAX
A0
READ
(burst of 4)
2
t KHCH
t KHKH
t KHIX
t CHCQV
t CHCQX
t CHQX1
t CHQV
3
t KHK#H
(Note 1)
Q00
A1
READ
(burst of 4)
4
t CHQX
Q01
t CHCQX
t CHQV
t CHCQV
Q02
5
Q03
READ/WRITE Timing
t CQHQV
t CHQX
Q10
6
NOP
t KHKL
Q11
Figure 6:
t KLKH t KHKH
Q12
t CQHQX
7
19
NOP
(Note 3)
Q13
2 MEG
1.8V V
A2
t CHQZ
8
WRITE
(burst of 4)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DVKH
t KHK#H
t KHDX
X
D20
8, 1 MEG
9
DD
D21
, HSTL, DDRIIb4 SRAM
t DVKH
t KHDX
D22
A3
WRITE
(burst of 4)
10
D23
X
D30
11
18, 512K
D31
DON’T CARE
D32
A4
READ
(burst of 4)
©2003 Micron Technology, Inc.
12
D33
X
13
36
UNDEFINED
Q40

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