MT57W1MH18J Micron Semiconductor Products, Inc., MT57W1MH18J Datasheet - Page 22

• Manufacturer Part Number: MT57W1MH18J
• Description: 18Mb Ddrii SRAM, 1.8V Vdd, Hstl, 4-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

EXTEST
to be executed whenever the instruction register is
loaded with all 0s. EXTEST is not implemented in this
SRAM TAP controller; therefore, this device is not
1149.1-compliant.
tion. When an EXTEST instruction is loaded into the
instruction register, the SRAM responds as if a
SAMPLE/PRELOAD instruction has been loaded.
EXTEST does not place the SRAM outputs (including
CQ and CQ#) in a High-Z state.
IDCODE
32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI
and TDO balls and allows the IDCODE to be shifted
out of the device when the TAP controller enters the
Shift-DR state. The IDCODE instruction is loaded into
the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
SAMPLE Z
scan register to be connected between the TDI and
TDO balls when the TAP controller is in a Shift-DR
state. It also places all SRAM outputs into a High-Z
state.
18Mb: 1.8V V
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
EXTEST is a mandatory 1149.1 instruction which is
The TAP controller does recognize an all-0 instruc-
The IDCODE instruction causes a vendor-specific,
The SAMPLE Z instruction causes the boundary
DD
, HSTL, DDRIIb4 SRAM
22
2 MEG
SAMPLE/PRELOAD
tion. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.
is not implemented, putting the TAP into the Update-
DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
BYPASS
instruction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between TDI and
TDO. The advantage of the BYPASS instruction is that
it shortens the boundary scan path when multiple
devices are connected together on a board.
Reserved
reserved for future use. Do not use these instructions.
SAMPLE/PRELOAD is a 1149.1 mandatory instruc-
Note that since the PRELOAD part of the command
When the BYPASS instruction is loaded in the
These instructions are not implemented but are
1.8V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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8, 1 MEG
DD
, HSTL, DDRIIb4 SRAM
X
18, 512K
©2003 Micron Technology, Inc.
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