MT57W1MH18J Micron Semiconductor Products, Inc., MT57W1MH18J Datasheet

MT57W1MH18J

Manufacturer Part Number

MT57W1MH18J

Description

18Mb Ddrii SRAM, 1.8V Vdd, Hstl, 4-Word Burst,

Manufacturer

Micron Semiconductor Products, Inc.

Datasheet

1.MT57W1MH18J.pdf (28 pages)

Current page: 1 of 28
Download datasheet (410Kb)

18Mb DDRII CIO SRAM

4-WORD BURST

Features

• DLL circuitry for accurate output data placement

• Pipelined, double data rate operation

• Common data input/output bus

• Fast clock to valid data times

• Full data coherency, providing most current data

• Four-tick burst for reduced-address frequency

• Two input clocks (K and K#) for precise DDR timing

• Two output clocks (C and C#) for precise flight time

• Optional-use echo clocks (CQ and CQ#) for flexible

• Simple control logic for easy depth expansion

• Internally self-timed, registered writes

• Core V

• Clock-stop capability with µs restart

• 13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA

• User-programmable impedance output

• JTAG boundary scan

NOTE:

18Mb: 1.8V V

MT57W1MH18J_H.fm – Rev. H, Pub. 3/03

Options

• Clock Cycle Timing

• Configurations

• Package

• Operating Temperature Range

1. A Part Marking Guide for the FBGA devices can be found on

at clock rising edges only

and clock skew matching—clock and data delivered

together to receiving device

receive data synchronization

(±0.1V) HSTL

package

Micron’s Web

3ns (333 MHz)

3.3ns (300 MHz)

4ns (250 MHz)

5ns (200 MHz)

6ns (167 MHz)

7.5ns (133 MHz)

2 Meg x 8

1 Meg x 18

165-ball, 13mm x 15mm FBGA

Commercial (0°C £ T

512K x 36

, HSTL, DDRIIb4 SRAM

= 1.8V (±0.1V); I/O V

site—http://www.micron.com/numberguide

£ +70°C)

Q = 1.5V to V

MT57W512H36J

MT57W1MH18J

MT57W2MH8J

Marking

None

-3.3

-7.5

-3

-4

-5

-6

2 MEG

Table 1:

General Description

SRAM employs high-speed, low-power CMOS designs

using an advanced 6T CMOS process.

advanced synchronous peripheral circuitry and a burst

counter. All synchronous inputs pass through registers

controlled by an input clock pair (K and K#) and are

latched on the rising edge of K and K#. The synchro-

nous inputs include all addresses, all data inputs,

active LOW load (LD#), read/write (R/W#), and active

LOW byte writes or nibble writes (BWx# or NWx#).

Write data is registered on the rising edges of both K

and K#. Read data is driven on the rising edge of C and

C#, if provided, or on the rising edge of K and K# if C

and C# are not provided.

(ZQ). Synchronous data outputs (Q, sharing the same

physical balls as the data inputs D) are tightly matched

MT57W2MH8J

MT57W1MH18J

MT57W512H36J

PART NUMBER

MT57W2MH8JF-xx

MT57W1MH18JF-xx

MT57W512H36JF-xx

The Micron

The DDR SRAM integrates an SRAM core with

Asynchronous inputs include impedance match

1.8V V

Figure 1: 165-Ball FBGA

8, 1 MEG

Valid Part Numbers

DDRII synchronous, pipelined burst

, HSTL, DDRIIb4 SRAM

DESCRIPTION

2 Meg x 8, DDRIIb4 FBGA

1 Meg x 18, DDRIIb4 FBGA

512K x 36, DDRIIb4 FBGA

18, 512K

Related parts for MT57W1MH18J

MT57W1MH18J Summary of contents

Page 1

... Operating Temperature Range Commercial (0°C £ T £ +70°C) A NOTE Part Marking Guide for the FBGA devices can be found on Micron’s Web site—http://www.micron.com/numberguide 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V MT57W2MH8J MT57W1MH18J MT57W512H36J . Table 1: ...

Page 2

... NOP cycles are not required when switching from a WRITE to a READ. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1. READ occurs after a WRITE cycle, address and data for the write are stored in registers. The write information must be stored because the SRAM cannot perform the last word write to the array without con- flicting with the read ...

Page 3

... The user can operate the part with fewer than 1,024 clock cycles, but optimal output impedance is not guaranteed. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Clock Considerations This device utilizes internal delay-locked loops for maximum output, data valid window. It can be placed into a stopped-clock state to minimize power with a modest restart time of 1,024 clock cycles ...

Page 4

... For 2 Meg 21 NWx separate nibble writes. For 1 Meg 18; BWx separate byte writes. For 512K 36; BWx separate byte writes. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 2: Functional Block Diagram 2 Meg Meg x 18; 512K ...

Page 5

... For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 3: Application Example R = 250Ω ...

Page 6

... Expansion address: 10A for 36Mb 5. Expansion address: 5B for 288Mb 6. NW0# controls writes to DQ0:DQ3 Note that the x8 does not permit random start address on the two least-significant address bits. SA and SA1 = 0 at the start of each address. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1. R/W# ...

Page 7

... R TDO TCK NOTE: 1. Expansion address: 2A for 72Mb 2. BW1#controls writes to DQ9:DQ17 3. Expansion address: 7A for 144Mb 4. Expansions address: 10A for 36Mb 5. Expansion address: 5B for 288Mb 6. BW0# controls writes to DQ0:DQ8 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1. R/W# BW1 ...

Page 8

... Expansion address: 2A for 144Mb 2. Expansion address: 3A for 36Mb 3. BW2# controls writes to DQ18:DQ26 4. BW1# controls writes to DQ9:DQ17 5. Expansion address: 10A for 72Mb 6. BW3# controls writes to DQ27:DQ35 7. BW0# controls writes to DQ0:DQ8 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1. R/W# BW2# ...

Page 9

... Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC DD Electrical Characteristics and Operating Conditions for range. V Supply Power Supply: GND. SS 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG HSTL, DDRIIb4 SRAM DD if the JTAG function is not used SS Q/2 ...

Page 10

... DESCRIPTION NC – No Connect: These balls are internally connected to the die, but have no function and may be left not connected to the board to minimize ball count. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG HSTL, DDRIIb4 SRAM DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 11

... SA0 and SA1 are internally advanced in accordance with the burst order table. Bus cycle is terminated after burst count = 4. 2. State transitions (LD# = LOW (LD# = HIGH (R/W# = HIGH (R/W# = LOW). 3. State machine, control timing sequence is controlled by K. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V SECOND ADDRESS THIRD ADDRESS (INTERNAL X01 X ...

Page 12

... This table illustrates operation for x18 devices. The x36 device operation is similar, except for the addition of BW2# (controls DQ18:DQ26) and BW3# (controls DQ27:DQ35). The x8 device operation is similar, except that NW0# con- trols DQ0:DQ3, and NW1# controls DQ4:DQ7. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V LD# R/W# K ...

Page 13

... DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 1) Voltage 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- ...

Page 14

... Input, Output Capacitance (DQ) Clock Capacitance Table 13: Thermal Resistance Note 13; notes appear following parameter tables on page 17 DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) Junction to Balls (Bottom) 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V £ +70° SYMBOL TYP -3 -3.3 ³ ...

Page 15

... CQ, CQ# HIGH to t CQHQV output valid CQ, CQ# HIGH to t CQHQX -0.25 output hold C HIGH to t CHQZ output High-Z C HIGH to t CHQX1 -0.45 output Low-Z Setup Times Address valid to t AVKH 0.40 K rising edge 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V -3.3 -4 3.47 3.30 4.20 4.00 5.25 5.00 0.20 0.20 0.20 1.32 1.60 2.00 1.32 1.60 2.00 1.49 1.80 2.20 1.49 1.80 2.20 1 ...

Page 16

... K, K# rising edge Hold Times K rising edge to t KHAX 0.40 address hold K rising edge to t control inputs KHIX 0.40 hold K, K# rising edge t KHDX 0.28 to data-in hold 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG X 1. 0.40 0.50 0.60 0.30 0.35 0.40 0.40 0.50 0.60 0.40 0.50 0.60 0.30 0.35 0.40 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 17

... Typical values are measured at V 1.5V, and temperature = 25°C. 11. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are com- pleted. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1. 12. Average I/O current and power is provided for OH informational purposes only and is not tested ...

Page 18

... Input rise and fall times...................................... 0.7ns Input timing reference levels .............................0.75V Output reference levels................................... V ZQ for 50 W impedance ....................................... 250 W Output load ..............................................See Figure 5 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X 1. HSTL, DDRIIb4 SRAM DD Output Load Equivalent ...

Page 19

... Outputs are disabled (High-Z) one clock cycle after a NOP. 3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to prevent bus contention. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 6: READ/WRITE Timing NOP ...

Page 20

... NOTE: The 0/1 next to each state represents the value of TMS at the rising edge of TCK. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK ...

Page 21

... TDI and TDO balls. This allows data to be shifted through the SRAM with mini- mal delay. The bypass register is set LOW (Vss) when the BYPASS instruction is executed. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X 1. HSTL, DDRIIb4 SRAM DD ...

Page 22

... The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller Shift-DR state. It also places all SRAM outputs into a High-Z state. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG HSTL, DDRIIb4 SRAM DD SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149 ...

Page 23

... NOTE and CH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in Figure 10. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG X 1.8V V Figure 9: TAP Timing ...

Page 24

... This table defines DC values for TAP control and data balls only. The DQ SRAM balls used in JTAG operation will have the DC values as defined in Table 9, “DC Electrical Characteristics and Operating Conditions,” on page 13. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V TAP AC Output Load Equivalent to 1.8V ...

Page 25

... Do Not Use: This instruction is reserved for future use. 111 BYPASS Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V ALL DEVICES DESCRIPTION 000 Revision number. 00def0wx0t0q0b0s0 ...

Page 26

... V , HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X 1. HSTL, DDRIIb4 SRAM DD BIT# FBGA BALL 37 10D 10C 40 11D 11B 44 11C 10B ...

Page 27

... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 11: 165-Ball FBGA 0.12 C ...

Page 28

... Rev. 3, Pub. 12/01, ADVANCE...................................................................................................................................12/01 • Changed AC Timing Rev. 2, Pub. 11/01, ADVANCE...................................................................................................................................11/01 • New ADVANCE data sheet 18Mb: 1. HSTL, DDRIIb4 SRAM DD MT57W1MH18J_H.fm – Rev. H, Pub. 3/03 2 MEG X 1.8V V test conditions for read to write ratio DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Related keywords

MT57W1MH18J datasheet
MT57W1MH18J data sheet
MT57W1MH18J pdf datasheet
MT57W1MH18J component
MT57W1MH18J part
MT57W1MH18J distributor
MT57W1MH18J RoHS
MT57W1MH18J datasheet download