MT28C6428P20 Micron Semiconductor Products, Inc., MT28C6428P20 Datasheet - Page 5

• Manufacturer Part Number: MT28C6428P20
• Description: 4 Meg X 16 Asynchronous/page Flash 512K X 16 SRAM Combo Memory
• Manufacturer: Micron Semiconductor Products, Inc.

BALL DESCRIPTIONS
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02
H6, G9, G8, G7,
H5, H4, G6, G5,
A8, A7, A6, A5,
67-BALL FBGA
B4, B6, B5, A4,
B3, G4, G3, E5,
F7, E8, E6, D7,
E10, C9, C10,
C8, B10, F8,
F9, F10, E9,
NUMBERS
C7, B9, B7
A3, C5
G10
H7
H9
D4
D8
C3
B8
E3
F5
F3
F4
DQ0–DQ15
SYMBOL
A0–A21
S_CE1#
F_WE#
F_WP#
S_WE#
F_OE#
S_OE#
S_UB#
F_CE#
F_RP#
S_CE2
S_LB#
Output
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE
Address Inputs: Inputs for the addresses during READ and WRITE
operations. Addresses are internally latched during READ and WRITE
cycles. Flash: A0–A21; SRAM: A0–A18.
Flash Chip Enable: Activates the device when LOW. When CE# is HIGH,
the device is disabled and goes into standby power mode.
Flash Output Enable: Enables Flash output buffers when LOW. When
F_OE# is HIGH, the output buffers are disabled.
Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle.
F_WE# is active LOW.
Reset. When F_RP# is a logic LOW, the device is in reset, which drives
the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH,
the device is in standard operation. When F_RP# transitions from logic
LOW to logic HIGH, the device resets all blocks to locked and defaults to
the read array mode.
Flash Write Protect. Controls the lock down function of the flexible
locking feature.
SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level
deselects the SRAM and reduces the power consumption to standby
levels.
SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level
deselects the SRAM and reduces the power consumption to standby
levels.
SRAM Output Enable: Enables SRAM output buffers when LOW. When
S_OE# is HIGH, the output buffers are disabled.
SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle.
S_WE# is active LOW.
SRAM Lower Byte: When LOW, it selects the SRAM address lower byte
(DQ0–DQ7).
SRAM Upper Byte: When LOW, it selects the SRAM address upper byte
(DQ8–DQ15).
Data Inputs/Outputs: Input array data on the second CE# and WE#
cycle during PROGRAM command. Input commands to the command
user interface when CE# and WE# are active. Output data when CE#
and OE# are active.
(continued on next page)
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
512K x 16 SRAM COMBO MEMORY
5
DESCRIPTION
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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