MT28C6428P20 Micron Semiconductor Products, Inc., MT28C6428P20 Datasheet - Page 20

• Manufacturer Part Number: MT28C6428P20
• Description: 4 Meg X 16 Asynchronous/page Flash 512K X 16 SRAM Combo Memory
• Manufacturer: Micron Semiconductor Products, Inc.

the completion of a WRITE, an ERASE can be resumed
by writing an ERASE RESUME command.
to check if the block has been erased successfully, us-
ing the CHECK BLOCK ERASE command. Two bus
cycles are required for this operation: one to set up the
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02
STATUS
BIT #
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
After an ERASE command completion, it is possible
WSMS
7
STATUS REGISTER BIT
WRITE STATE MACHINE STATUS (WSMS) Check write state machine bit first to determine word
1 = Ready
0 = Busy
ERASE SUSPEND STATUS (ESS)
1 = BLOCK ERASE Suspended
0 = BLOCK ERASE in
ERASE/CHECK BLOCK ERASE
STATUS (ES)
1 = Error in BLOCK ERASE/
0 = Successful BLOCK ERASE
PROGRAM STATUS (PS)
1 = Error in PROGRAM
0 = Successful PROGRAM
F_V
1 = F_V
0 = F_V
PROGRAM SUSPEND STATUS (PSS)
1 = PROGRAM Suspended
0 = PROGRAM in Progress/Completed
BLOCK LOCK STATUS (BLS)
1 = PROGRAM/ERASE Attempted on a
0 = No Operation to Locked Blocks
RESERVED FOR FUTURE
ENHANCEMENT
PP
Progress/Completed
CHECK BLOCK ERASE
Locked Block; Operation Aborted
STATUS (V
PP
PP
ESS
Low Detect, Operation Abort of the F_V
= OK
6
PP
S)
ES
5
Status Register Bit Definition
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
PS
4
When ERASE SUSPEND is issued, WSM halts execution and
“1” until an ERASE RESUME command is issued.
has applied the maximum number of erase pulses to the
block and is still unable to verify successful block erasure.
When this bit is set to “1” and CHECK BLOCK ERASE CONFIRM
is issued, WSM has checked the block for its erase state, and
When this bit is set to “1,” WSM has attempted but failed to
program a word.
When PROGRAM SUSPEND is issued, WSM halts execution
“1” until a PROGRAM RESUME command is issued.
If a PROGRAM or ERASE operation is attempted to one of
the locked blocks, this is set by the WSM. The operation
specified is aborted, and the device is returned to read status
This bit is reserved for future use.
program or block erase completion, before checking
program or erase status bits.
sets both WSMS and ESS bits to “1.” ESS bit remains set to
When this bit is set to “1” and ERASE CONFIRM is issued, WSM
the block is not erased.
The F_V
after the program or erase command sequences have been
entered and informs the system if F_V
level is also checked before the PROGRAM/ERASE operation
is verified by the WSM. A factory option allows PROGRAM or
ERASE at 0V, in which case SR3 is held at “0.”
and sets both WSM and PSS bits to “1.” PSS bit remains set to
mode.
Table 8
20
512K x 16 SRAM COMBO MEMORY
PP
CHECK BLOCK ERASE and the second one to start the
execution of the command. If after the operation the
bit SR5 is set to 0 the operation has been completed
succesfully, if it is set to 1, there has been an error
during the BLOCK ERASE operation.
status bit does not provide continuous indication
PP
V
PP
3
level. The WSM interrogates the F_V
S
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
PSS
2
PP
BLS
< 0.9V. The F_V
1
©2002, Micron Technology, Inc.
ADVANCE
PP
level only
R
0
PP