MT28C6428P20 Micron Semiconductor Products, Inc., MT28C6428P20 Datasheet - Page 10

• Manufacturer Part Number: MT28C6428P20
• Description: 4 Meg X 16 Asynchronous/page Flash 512K X 16 SRAM Combo Memory
• Manufacturer: Micron Semiconductor Products, Inc.

FLASH MEMORY OPERATING MODES
COMMAND STATE MACHINE
chine (CSM) using standard microprocessor write tim-
ings. The CSM acts as an interface between external
microprocessors and the internal write state machine
(WSM). The available commands are listed in Table 3,
their definitions are given in Table 4 and their descrip-
tions in Table 5. Program and erase algorithms are au-
tomated by the on-chip WSM. Table 7 shows the CSM
transition states.
tered, the WSM executes the appropriate algorithm,
which generates the necessary timing signals to con-
trol the device internally. A command is valid only if the
exact sequence of WRITEs is completed. After the WSM
completes its task, the write state machine status
(WSMS) bit (SR7) (see Table 8) is set to a logic HIGH
level (V
mand set again.
OPERATIONS
dard JEDEC 8-bit command code with conventional
microprocessor timings into an on-chip CSM through
I/Os DQ0–DQ7. The number of bus cycles required to
activate a command is typically one or two. The first
operation is always a WRITE. Control signals F_CE#
and F_WE# must be at a logic LOW level (V
and F_RP# must be at logic HIGH (V
operation, when needed, can be a WRITE or a READ
depending upon the command. During a READ opera-
tion, control signals F_CE# and F_OE# must be at a
logic LOW level (V
logic HIGH (V
modes: write, read, reset, standby, and output disable.
cuitry initializes the chip to a read array mode of opera-
tion. Changing the mode of operation requires that a
command code be entered into the CSM. For each one
of the two Flash memory partitions, an on-chip status
register is available. These two registers allow the moni-
toring of the progress of various operations that can
take place on a memory bank. One of the two status
registers is interrogated by entering a READ STATUS
REGISTER command onto the CSM (cycle 1), specify-
ing an address within the memory partition boundary,
and reading the register data on I/O pins DQ0–DQ7
(cycle 2). Status register bits SR0-SR7 correspond to
DQ0–DQ7 (see Table 8).
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02
Commands are issued to the command state ma-
Once a valid PROGRAM/ERASE command is en-
Device operations are selected by entering a stan-
Table 7 illustrates the bus operations for all the
When the device is powered up, internal reset cir-
IH
), allowing the CSM to respond to the full com-
IH
).
IL
), and F_WE# and F_RP# must be at
IH
). The second
IL
), and F_OE#
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
10
512K x 16 SRAM COMBO MEMORY
COMMAND DEFINITION
the WSM executes an internal algorithm, generating
the necessary timing signals to program, erase, and
verify data. See Table 4 for the CSM command defini-
tions and data for each of the bus cycles.
STATUS REGISTER
whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored
by toggling F_OE# and F_CE# and reading the result-
ing status code on I/Os DQ0–DQ7. The high-order I/Os
(DQ8–DQ15) are set to 00h internally, so only the low-
order I/Os (DQ0–DQ7) need to be interpreted. Address
lines select the status register pertinent to the selected
memory partition.
COMMAND
DQ0–DQ7
Command State Machine Codes For
Once a specific command code has been entered,
The status register allows the user to determine
B0h
C0h
D0h
D1h
10h
20h
40h
50h
60h
60h
70h
90h
98h
FFh
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Device Mode Selection
CODE ON DEVICE MODE
Accelerated Programming Algorithm
(APA)
Block erase setup
Program setup
Clear status register
Protection configuration setup
Enable/disable deep power-down
Read status register
Read protection configuration
register
Read query
Program/erase suspend
Protection register program/lock
Program/erase resume – erase
confirm
Check block erase confirm
Read array
Table 3
©2002, Micron Technology, Inc.
ADVANCE