HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 48

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HFC-SPCI

Manufacturer Part Number
HFC-SPCI
Description
Isdn S/t HDLC Basic Rate Controller
Manufacturer
Cologne Chip AG
Datasheet
All specifications are for 2.048 Mb/s Streams and f
6.4
Timing diagram 2: EEPROM access
*)
$( _V &$
SYMBOL
t
t
t
SYMBOL
f
t
t
t
t
t
t
t
t
SToD
STiS
STiH
SCL
HD:STA
LOW
HIGH
SU:STA
HD:DAT
SU
DH
SCL
EEPROM access
with 33 MHz PCI clock
STIO1 Delay Level 2 Output
STIO2 Set Up Time
Serial Clock Frequency
Serial Clock Period
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
Output Data Change after Clock
Data In Setup Time
STIO2 Hold Time
Data In Hold Time
CHARACTERISTICS
CHARACTERISTICS
CLK
= 12.288 MHz.
MIN.
20 ns
30 ns
2 ns
6URbeQbi !)))
32.2 KHz
125 ns
1 / f
100 ns
100 ns
MAX
¾
½
½
¾
TYP.
10 ns
30ns
t
t
t
t
SCL
SCL
SCL
SCL
SCL
*)

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