HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 24

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

For each FIFO an array of Z1 and Z2 counters is available. The offset of the counters to the Memory
Window Base Address (MWBA) can be calculated as shown in the following table.
*)
Fx is either F1 or F2. F1 is used for input data in transmit FIFOs, F2 is used for output data in receive
FIFOs.
3.4.2
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FIFO
B1-transmit
B1-receive
B2-transmit
B2-receive
D-transmit
D-receive
FIFO
B1-transmit
B1-receive
B2-transmit
B2-receive
D-transmit
D-receive
These counters are handled by the HFC-S PCI automatically and must not be written by software.
FIFO data location in Memory Window
Counter
Starting at Offset
Z2
Z1
Z2
Z1
Z2
Z1
Z1
Z2
Z1
Z2
Z1
Z2
*)
*)
*)
*)
*)
*)
0200h
4200h
2200h
6200h
0000h
4000h
2000h + (Fx * 4)
2000h + (Fx * 4) + 2
6000h + (Fx * 4)
6000h + (Fx * 4) + 2
2100h + (Fx * 4)
2100h + (Fx * 4) + 2
6100h + (Fx * 4)
6100h + (Fx * 4) + 2
2080h + (Fx * 4)
2080h + (Fx * 4) + 2
6080h + (Fx * 4)
6080h + (Fx * 4) + 2
Offset to Memory Window
Base Address
Ending at Offset
1FFFh
5FFFh
3FFFh
7FFFh
01FFh
41FFh
Counter Size
Z-counters value
in Bytes
Offset to add to
2
2
2
2
2
2
2
2
2
2
2
2
0000h
4000h
0000h
4000h
2000h
6000h
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