HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 40

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

$ _V &$
Name
INT_S1
INT_S2
*
Reading the INT_S1 or INT_S2 register resets all active read interrupts in the INT_S1 or INT_S2
register. New interrupts may occur during read. These interrupts are reported at the next read of
INT_S1 or INT_S2.
All interrupt bits are reported regardless of the mask registers settings (INT_M1 and INT_M2).
The mask register settings only influence the interrupt output condition.
The interrupt output goes inactive during the read of INT_S1 or INT_S2. If interrupts occur during
this read the interrupt line goes active immediately after the read is finished. So processors with
level or transition triggered interrupt inputs can be connected.
important!
Addr.
7Ch
78h
Bits
6..3
0
1
2
3
4
5
6
7
0
1
2
7
r/w Function
r
r
r
r
r
r
r
r
r
r
r
r
r
B1-channel interrupt status in transmit direction
B2-channel interrupt status in transmit direction
in HDLC mode:
in transparent mode:
D-channel interrupt status in transmit direction
'1'
B1-channel interrupt status in receive direction
B2-channel interrupt status in receive direction
in HDLC mode:
in transparent mode:
D-channel interrupt status in receive direction
'1'
TE/NT state machine interrupt status
'1' state of state machine changed
timer interrupt status
'1' timer is elapsed
processing/non processing transition interrupt status
'1'
GCI I-change interrupt
'1'
receiver ready (RxR) of monitor channel
'1'
unused, '0'
'1' fatal error: synchronisation lost. PCI performance too low
'1' a complete frame has been transmitted, the frame counter
'1' interrupt as selected in TRM register bits 1..0
'1' a complete frame has been transmitted, the frame counter
'1' interrupt as selected in TRM register bits 1..0
for HFC-S PCI. Only soft reset recovers from this situation.
F2 has been incremented
a complete frame was transmitted, the frame counter
F2 was incremented
F1 has been incremented
a complete frame was received, the frame counter
F1 was incremented
The HFC-S PCI has changed from processing to non
processing state.
a different I-value on GCI was detected
2 monitor bytes have been received
6URbeQbi !)))