HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 37

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

4.4
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Name
CIRM
FIFO_EN
Register bit description of auxiliary and cross data registers
Addr.
60h
44h
Bits
2..0
5..4
5..0
7..6
3
6
7
r/w Function
w
w
w
w
w
w
w
defines the length of the auxiliary port access:
Value
000b
001b
010b
011b
100b
101b
110b
111b
soft reset, similar as hardware reset; the registers CIP, CIRM
and CTMT are not changed. The PCI interface is not reset.
The reset is active until the bit is cleared.
'0' deactivate reset (reset default)
'1' activate reset
must be '0'
select bit order for B1 channel
'0'
'1'
select bit order for B2 channel
'0'
'1'
FIFO enable/disable ('1' = enable (reset default))
Bit
0
1
2
3
4
5
The enable/disable change becomes valid between 0 and
250µs after the bit has been written. All PCI bus accesses and
FIFO activities are disabled for the selected FIFOs. To avoid
unnecessary PCI transfers all unused FIFOs should be
disabled.
At least one FIFO (usually D-receive) must be enabled.
unused, should be '0'
normal read/write data operation
reverse bit order read/write data operation
normal read/write data operation
reverse bit order read/write data operation
FIFO
B1-transmit
B1-receive
B2-transmit
B2-receive
D-transmit
D-receive
11
13
15
Cycle time (AUX_WR or AUX_RD low)
1
3
5
7
9
PCI-Clock
PCI-Clocks
PCI-Clocks
PCI-Clocks
PCI-Clocks
PCI-Clocks
PCI-Clocks
PCI-Clocks
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