HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 21

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HFC-SPCI

Manufacturer Part Number
HFC-SPCI
Description
Isdn S/t HDLC Basic Rate Controller
Manufacturer
Cologne Chip AG
Datasheet
3.3
Timer
The HFC-S PCI includes a timer with interrupt capability. The timer counts F0IO pulses. So the timer
counter is incremented every 125µs. It can be reset by bit 7 of of the CTMT register. Furthermore the
timer is reset at every HFC-S PCI access when bit 5 of the CTMT register is set. Seven different timer
values can be selected.
6URbeQbi !)))
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